公开(公告)号：US06962857B1

公开(公告)日：2005-11-08

申请号：US10358966

申请日：2003-02-05

申请人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

发明人： Minh-Van Ngo ,  Ming-Ren Lin ,  Eric N. Paton ,  Haihong Wang ,  Qi Xiang ,  Jung-Suk Goo

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。 低温过程可以是LPCVD。 可以使用退火步骤来形成衬垫。

公开(公告)号：US06730576B1

公开(公告)日：2004-05-04

申请号：US10335447

申请日：2002-12-31

申请人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

发明人： Haihong Wang ,  Paul R. Besser ,  Jung-Suk Goo ,  Minh V. Ngo ,  Eric N. Paton ,  Qi Xiang

IPC分类号： H01L21762

CPC分类号： H01L29/7833 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.

摘要翻译： 应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。 在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。 两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。 因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。 在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

公开(公告)号：US06800910B2

公开(公告)日：2004-10-05

申请号：US10335474

申请日：2002-12-31

申请人： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

发明人： Ming-Ren Lin ,  Jung-Suk Goo ,  Haihong Wang ,  Qi Xiang

IPC分类号： H01L27105

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78603 ,  H01L29/78687

摘要： A FinFET device employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. An epitaxial layer of silicon is then formed on the silicon germanium FinFET body. A strain is induced in the epitaxial silicon as a result of the different dimensionalities of intrinsic silicon and of the silicon germanium crystal lattice that serves as the template on which the epitaxial silicon is grown. Strained silicon has an increased carrier mobility compared to relaxed silicon, and as a result the epitaxial strained silicon provides increased carrier mobility in the FinFET. A higher driving current can therefore be realized in a FinFET employing a strained silicon channel layer.

摘要翻译： FinFET器件采用应变硅来增强载流子迁移率。 在一种方法中，FinFET体从覆盖在电介质层上的硅锗层（SiGe）构图。 然后在硅锗FinFET体上形成硅的外延层。 由于本征硅和作为外延硅生长的模板的硅锗晶格的不同维度，在外延硅中引起应变。 与松弛硅相比，应变硅具有增加的载流子迁移率，结果外延应变硅在FinFET中提供增加的载流子迁移率。 因此，可以在采用应变硅沟道层的FinFET中实现更高的驱动电流。

公开(公告)号：US07170084B1

公开(公告)日：2007-01-30

申请号：US10872707

申请日：2004-06-21

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US06902991B2

公开(公告)日：2005-06-07

申请号：US10282513

申请日：2002-10-24

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/337 ,  H01L29/10 ,  H01L21/04

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/66893

摘要： A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

摘要翻译： 在硅锗层上生长应变硅层，并且在单个连续原位沉积工艺中，在应变硅层上生长第二层硅锗。 硅锗的两层可以用应变硅原位生长。 这种结构在应变硅层的两侧有效地提供了两个基板，以支撑应变硅层的拉伸应变，并且抵抗可能在加工过程中温度变化引起的失配位错的形成。 因此，可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。 覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持，以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

公开(公告)号：US06756276B1

公开(公告)日：2004-06-29

申请号：US10335522

申请日：2002-12-31

申请人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

发明人： Qi Xiang ,  Jung-Suk Goo ,  Haihong Wang

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

摘要翻译： 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

公开(公告)号：US07923785B2

公开(公告)日：2011-04-12

申请号：US10643461

申请日：2003-08-18

申请人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

发明人： Qi Xiang ,  Boon-Yong Ang ,  Jung-Suk Goo

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/02 ,  H01L29/4925 ,  H01L29/513 ,  H01L29/78 ,  H01L29/7845 ,  Y10S438/938

摘要： According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

摘要翻译： 根据一个示例性实施例，位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质，其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极，其中第一栅电极具有第二热膨胀系数，并且其中第二热膨胀系数不同于第一热膨胀系数，从而导致 增加FET中的载流子迁移率。 例如，第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。

公开(公告)号：US07138302B2

公开(公告)日：2006-11-21

申请号：US10755763

申请日：2004-01-12

申请人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

发明人： Qi Xiang ,  James N. Pan ,  Jung-Suk Goo

IPC分类号： H01L21/335 ,  H01L21/84 ,  H01L21/338 ,  H01L21/8249 ,  H01L27/01

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842

摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

摘要翻译： 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。

公开(公告)号：US07078299B2

公开(公告)日：2006-07-18

申请号：US10654631

申请日：2003-09-03

申请人： Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

发明人： Witold P. Maszara ,  Jung-Suk Goo ,  James N. Pan ,  Qi Xiang

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  A61F5/3776 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S438/933

摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.

摘要翻译： 使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成 特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

公开(公告)号：US20050153486A1

公开(公告)日：2005-07-14

申请号：US10755763

申请日：2004-01-12

申请人： Qi Xiang ,  James Pan ,  Jung-Suk Goo

发明人： Qi Xiang ,  James Pan ,  Jung-Suk Goo

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842

摘要： An exemplary embodiment relates to a method of FinFET channel structure formation. The method can include providing a compound semiconductor layer above an insulating layer, providing a trench in the compound semiconductor layer, and providing a strained semiconductor layer above the compound semiconductor layer and within the trench. The method can also include removing the strained semiconductor layer from above the compound semiconductor layer, thereby leaving the strained semiconductor layer within the trench and removing the compound semiconductor layer to leave the strained semiconductor layer and form the fin-shaped channel region.

摘要翻译： 示例性实施例涉及FinFET沟道结构形成的方法。 该方法可以包括在绝缘层之上提供化合物半导体层，在化合物半导体层中提供沟槽，并在化合物半导体层之上和沟槽内提供应变半导体层。 该方法还可以包括从化合物半导体层上方去除应变半导体层，从而将应变半导体层留在沟槽内，并去除化合物半导体层以留下应变半导体层并形成鳍状沟道区。