公开(公告)号：US20240105243A1

公开(公告)日：2024-03-28

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong XU ,  Satish KRISHNAMOORTHY ,  Boris Dimitrov ANDREEV ,  Patrick ISAKANIAN ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Ravindra Arvind KHEDKAR

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US20250119059A1

公开(公告)日：2025-04-10

申请号：US18481657

申请日：2023-10-05

Applicant: Qualcomm Incorporated

Inventor： Boris Dimitrov ANDREEV ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Yong XU ,  Satish KRISHNAMOORTHY

IPC: H02M3/04 ,  H04W52/02

Abstract: In some aspects, an electronic device may detect a start of a voltage ramp transition period associated with changing a voltage at which an integrated circuit operates from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage causes changes to one or more parameters that impact performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may trigger, responsive to detecting the start of the voltage ramp transition period, a dynamic calibration mode that compensates for the changes to the one or more parameters that impact the performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may exit the dynamic calibration mode responsive to detecting an end of the voltage ramp transition period. Numerous other aspects are described.

公开(公告)号：US20250077113A1

公开(公告)日：2025-03-06

申请号：US18644294

申请日：2024-04-24

Applicant: QUALCOMM Incorporated

Inventor： Farrukh AQUIL ,  Boris Dimitrov ANDREEV ,  Joon Young PARK ,  Vishal MISHRA ,  Yong XU

IPC: G06F3/06 ,  G06N20/00

Abstract: Various aspects of the present disclosure generally relate to memory devices. In some aspects, a volatile memory device may receive, from a host device, a clock (CK) signal. The memory device may receive, from the host device, a command address (CA) signal associated with a continuous long burst pseudo-random binary sequence (PRBS) pattern. The memory device may perform a command bus training (CBT) based at least in part on the CA signal in relation to the CK signal. The memory device may provide, to the host device, pass or fail results associated with the CBT. Numerous other aspects are described.

公开(公告)号：US20210303020A1

公开(公告)日：2021-09-30

申请号：US16832855

申请日：2020-03-27

Applicant: Qualcomm Incorporated

Inventor： Farrukh AQUIL ,  Mahallingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Yong XU

IPC: G06F1/08 ,  G06F13/16 ,  G06F1/12

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.

公开(公告)号：US20240161808A1

公开(公告)日：2024-05-16

申请号：US17988186

申请日：2022-11-16

Applicant: QUALCOMM Incorporated

Inventor： Yong XU ,  Boris Dimitrov ANDREEV ,  Yuxin LI ,  Vikas MAHENDIYAN

IPC: G11C11/4076 ,  H03K19/20 ,  H03L7/081

CPC classification number: G11C11/4076 ,  H03K19/20 ,  H03L7/0812

Abstract: In certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an OR gate having a first input, a second input, and an output, wherein the output of the OR gate is coupled to the clock path. The system also includes a first clock gating circuit coupled between the first clock source and the first input of the OR gate, and a second clock gating circuit coupled between the second clock source and the second input of the OR gate.

公开(公告)号：US20210233579A1

公开(公告)日：2021-07-29

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  Vaishnav SRINIVAS ,  Mahalingam NAGARAJAN ,  Yong XU

IPC: G11C11/4076 ,  G06F13/42 ,  G11C11/409 ,  G11C7/10

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US20140321227A1

公开(公告)日：2014-10-30

申请号：US13901511

申请日：2013-05-23

Applicant: QUALCOMM Incorporated

Inventor： Zeeshan SYED ,  Nan CHEN ,  Yong XU ,  Michael Thomas FERTSCH ,  Boris ANDREEV ,  Zhiqin CHEN ,  Chang Ki KWON

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract translation: 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。