公开(公告)号：US20140321227A1

公开(公告)日：2014-10-30

申请号：US13901511

申请日：2013-05-23

Applicant: QUALCOMM Incorporated

Inventor： Zeeshan SYED ,  Nan CHEN ,  Yong XU ,  Michael Thomas FERTSCH ,  Boris ANDREEV ,  Zhiqin CHEN ,  Chang Ki KWON

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Abstract translation: 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。

公开(公告)号：US20230396247A1

公开(公告)日：2023-12-07

申请号：US18327832

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Chiu Keung TANG ,  Zhiqin CHEN

IPC: H03K17/687 ,  G11C27/02 ,  G11C7/06

CPC classification number: H03K17/6872 ,  H03K17/6874 ,  G11C27/02 ,  G11C7/06 ,  H03K19/20

Abstract: A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

公开(公告)号：US20230246885A1

公开(公告)日：2023-08-03

申请号：US17589782

申请日：2022-01-31

Applicant: QUALCOMM Incorporated

Inventor： Miao LI ,  Zhiqin CHEN ,  Yu SONG ,  Hongmei LIAO ,  Zhi ZHU ,  Hao LIU ,  Lejie LU

IPC: H04L25/03 ,  H03F3/45

CPC classification number: H04L25/03057 ,  H03F3/45475

Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

公开(公告)号：US20230170911A1

公开(公告)日：2023-06-01

申请号：US17537264

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Burcin Serter ERGUN ,  Julian PUSCAR ,  Zhiqin CHEN ,  Dewanshu Chhagan SEWAKE

IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099 ,  H03L7/08 ,  H04L7/00

CPC classification number: H03L7/1974 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0807 ,  H04L7/0079

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.