公开(公告)号：US20200280295A1

公开(公告)日：2020-09-03

申请号：US16452003

申请日：2019-06-25

Applicant: QUALCOMM Incorporated

Inventor： Siqi FAN ,  Li SUN ,  Dong REN ,  Miao LI ,  Jie XU

IPC: H03H5/00

Abstract: Aspects of the disclosure are directed to a low noise T-coil design. In accordance with one aspect, an input/output (I/O) circuit includes a first T-coil, wherein the first T-coil includes a first set of two inductors connected to each other in series arranged to accommodate a first current flow to produce a first magnetic field with a first perpendicular direction; and a second T-coil, wherein the second T-coil includes a second set of two inductors connected to each other in series arranged to accommodate a second current flow to produce a second magnetic field with a second perpendicular direction; and wherein the second magnetic field cancels the first magnetic field.

公开(公告)号：US20230246885A1

公开(公告)日：2023-08-03

申请号：US17589782

申请日：2022-01-31

Applicant: QUALCOMM Incorporated

Inventor： Miao LI ,  Zhiqin CHEN ,  Yu SONG ,  Hongmei LIAO ,  Zhi ZHU ,  Hao LIU ,  Lejie LU

IPC: H04L25/03 ,  H03F3/45

CPC classification number: H04L25/03057 ,  H03F3/45475

Abstract: A receiver has a first equalizer circuit that includes a first stage having a source degeneration circuit and a trans-impedance amplifier (TIA). The source degeneration circuit includes a resistor coupled in parallel with a capacitor. The TIA includes an embedded variable gain amplifier with a gain controlled by feedback resistors. Each feedback resistor is coupled between input and output of the TIA. In some implementations, the receiving circuit has a second equalizer circuit coupled in series with the first equalizer circuit. The second equalizer circuit includes a first stage having a source degeneration circuit and a TIA. The source degeneration circuit in the second equalizer circuit has a source degeneration resistor coupled in parallel with a source degeneration capacitor and the TIA includes an embedded variable gain amplifier whose gain is controlled by feedback resistors coupled between input and output of the TIA in the second equalizer circuit.

公开(公告)号：US20210175875A1

公开(公告)日：2021-06-10

申请号：US17101685

申请日：2020-11-23

Applicant: QUALCOMM Incorporated

Inventor： Miao LI ,  Yu SONG ,  Jie XU

IPC: H03K3/012 ,  H03F3/45 ,  H03K17/687 ,  G11C11/4093

Abstract: A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

公开(公告)号：US20210175868A1

公开(公告)日：2021-06-10

申请号：US17099183

申请日：2020-11-16

Applicant: QUALCOMM Incorporated

Inventor： Miao LI ,  Li SUN ,  Hao LIU

IPC: H03G5/16 ,  H03F3/04 ,  H03G3/30

Abstract: A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

公开(公告)号：US20160204749A1

公开(公告)日：2016-07-14

申请号：US14595106

申请日：2015-01-12

Applicant: QUALCOMM Incorporated

Inventor： Miao LI ,  Li SUN ,  Zhi ZHU

IPC: H03F1/30 ,  H03F3/45 ,  H03G3/30

CPC classification number: H03F1/30 ,  H03F3/45076 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/4565 ,  H03F3/45766 ,  H03F2200/447 ,  H03F2200/543 ,  H03F2203/45048 ,  H03F2203/45101 ,  H03F2203/45116 ,  H03F2203/45244 ,  H03F2203/45456 ,  H03G1/0029 ,  H03G3/3036 ,  H03K19/00384 ,  H03K19/018528

Abstract: An apparatus is provided. The apparatus includes a calibration circuit configured to generate a reference signal and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit may be configured to generate the reference signal independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal may be generated independently of the at least one differential circuit.

Abstract translation: 提供了一种装置。 该装置包括被配置为产生参考信号的校准电路和至少一个差分电路，每个差分电路被配置为基于参考信号在校准的跨导处超过过程或条件变化进行操作。 校准电路可以被配置为独立于至少一个差分电路产生参考信号。 提供了一种用于操作至少一个差分电路的方法。 该方法包括产生参考信号并且以校准的跨导或基于参考信号的过程或条件变化获得的增益来操作至少一个差分电路。 参考信号可以独立于至少一个差分电路产生。