公开(公告)号：US20230170911A1

公开(公告)日：2023-06-01

申请号：US17537264

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Burcin Serter ERGUN ,  Julian PUSCAR ,  Zhiqin CHEN ,  Dewanshu Chhagan SEWAKE

IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099 ,  H03L7/08 ,  H04L7/00

CPC classification number: H03L7/1974 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0807 ,  H04L7/0079

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.