公开(公告)号：US20210233579A1

公开(公告)日：2021-07-29

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  Vaishnav SRINIVAS ,  Mahalingam NAGARAJAN ,  Yong XU

IPC: G11C11/4076 ,  G06F13/42 ,  G11C11/409 ,  G11C7/10

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US20170236567A1

公开(公告)日：2017-08-17

申请号：US15142316

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  MICHAEL DROP ,  VAISHNAV SRINIVAS ,  PHILIP CLOVIS

IPC: G11C7/10 ,  G06F13/16 ,  G06F13/42 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US20190041941A1

公开(公告)日：2019-02-07

申请号：US15668554

申请日：2017-08-03

Applicant: QUALCOMM INCORPORATED

Inventor： VINOD CHAMARTY ,  TRANG NGUYEN ,  EDWIN JOSE ,  XIN KANG ,  SEAN SWEENEY ,  MICHAEL DROP ,  BORIS ANDREEV ,  FARRUKH AQUIL

IPC: G06F1/32 ,  H04W52/02

Abstract: Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

公开(公告)号：US20170236572A1

公开(公告)日：2017-08-17

申请号：US15142306

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  MICHAEL DROP ,  VAISHNAV SRINIVAS ,  PHILIP CLOVIS

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received. MRW is either ignored or implemented by the first DRAM.