公开(公告)号：US20240038672A1

公开(公告)日：2024-02-01

申请号：US17877156

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Mahalingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Nitin JUNEJA ,  Christophe AVOINNE ,  Xavier Loic LELOUP ,  Michael David JAGER ,  Charles David PAYNTER ,  Joon Young PARK

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/14132 ,  H01L24/81 ,  H01L2224/81815

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

公开(公告)号：US20210233579A1

公开(公告)日：2021-07-29

申请号：US16752442

申请日：2020-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： FARRUKH AQUIL ,  Vaishnav SRINIVAS ,  Mahalingam NAGARAJAN ,  Yong XU

IPC: G11C11/4076 ,  G06F13/42 ,  G11C11/409 ,  G11C7/10

Abstract: Signal timing drift in a synchronous dynamic random access memory (SDRAM) system may be compensated for by performing write signal timing training using a multi-purpose command (MPC) first-in-first-out (FIFO) write and MPC FIFO read at periodic intervals interspersed with mission-mode SDRAM traffic. The test result samples obtained from the write signal timing training may be analyzed independently of mission-mode SDRAM traffic. The mission-mode timing of the SDRAM data bit signals relative to the SDRAM write clock signal may be adjusted based on the analysis.

公开(公告)号：US20210303020A1

公开(公告)日：2021-09-30

申请号：US16832855

申请日：2020-03-27

Applicant: Qualcomm Incorporated

Inventor： Farrukh AQUIL ,  Mahallingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Yong XU

IPC: G06F1/08 ,  G06F13/16 ,  G06F1/12

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.

公开(公告)号：US20150332735A1

公开(公告)日：2015-11-19

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio CHUN ,  Vaishnav SRINIVAS ,  David Ian WEST ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Jason THURSTON

IPC: G11C5/14 ,  G06F11/07

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract translation: 通过多相多路存储器总线通过片上系统（SoC）写入和读取动态随机存取存储器（DRAM）的功耗基于误码率（BER）和一个或多个阈值进行优化。 可以测量误码率（BER）并用于控制参数以实现功耗和精度之间的最佳平衡。 在正常任务模式操作与实时流量期间，执行误码率（BER）测量，有意添加抖动和检查阈值。 错误检测可以涵盖具有二进制数据块的每个存储器数据事务。

公开(公告)号：US20150194959A1

公开(公告)日：2015-07-09

申请号：US14663303

申请日：2015-03-19

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio CHUN ,  Sumeet SETHI ,  John EATON ,  Vinodh CUPPU ,  Vikram ARORA ,  Vaishnav SRINIVAS ,  Asim Muhammed MUNEER ,  Isaac BERK

IPC: H03K19/0175 ,  G06F13/40

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。