公开(公告)号：US20240038672A1

公开(公告)日：2024-02-01

申请号：US17877156

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Mahalingam NAGARAJAN ,  Vaishnav SRINIVAS ,  Nitin JUNEJA ,  Christophe AVOINNE ,  Xavier Loic LELOUP ,  Michael David JAGER ,  Charles David PAYNTER ,  Joon Young PARK

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/14132 ,  H01L24/81 ,  H01L2224/81815

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

公开(公告)号：US20210065772A1

公开(公告)日：2021-03-04

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20250094264A1

公开(公告)日：2025-03-20

申请号：US18470333

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Mohsin RIAZ ,  Tamer KAFAFI ,  Xavier Loic LELOUP ,  Mosaddiq SAIFUDDIN

IPC: G06F11/07 ,  G06F9/30

Abstract: Various embodiments include methods and devices for implementing a scan dump of memory subsystem cores. Embodiments may include enabling a scan dump path of the memory subsystem during a computing device crash reset flow, the scan dump path comprising at least one memory controller having at least one scan dump logic module, a scan dump network on chip (NoC) module, and at least one scan dump data bus connecting the at least one scan dump logic module and the scan dump NoC, and initializing a scan mode for a memory path of the memory subsystem and for a low power memory path of the memory subsystem.

公开(公告)号：US20210064463A1

公开(公告)日：2021-03-04

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.