公开(公告)号：US20210065772A1

公开(公告)日：2021-03-04

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20210064463A1

公开(公告)日：2021-03-04

申请号：US16944110

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

公开(公告)号：US20200321051A1

公开(公告)日：2020-10-08

申请号：US16907103

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US20190026028A1

公开(公告)日：2019-01-24

申请号：US15658370

申请日：2017-07-24

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio CHUN ,  Jungwon SUH ,  Michael Hawjing LO

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/4094

Abstract: Disclosed are techniques for minimizing performance degradation due to refresh operations in a dynamic volatile memory sub-system. In an aspect, a refresh scheduler coupled to the dynamic volatile memory sub-system generates a batch memory refresh command comprising an identification of a plurality of rows of each of one or more banks of the dynamic volatile memory sub-system to refresh, and issues the batch memory refresh command to the dynamic volatile memory sub-system.

公开(公告)号：US20220027067A1

公开(公告)日：2022-01-27

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Dexter Tamio CHUN ,  Michael Hawjing LO ,  Shyamkumar THOZIYOOR ,  Ravindra KUMAR

IPC: G06F3/06 ,  G06F12/0875

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US20210343331A1

公开(公告)日：2021-11-04

申请号：US17377799

申请日：2021-07-16

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US20190221252A1

公开(公告)日：2019-07-18

申请号：US16362427

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

IPC: G11C11/406 ,  G11C7/10

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.