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    MEMORY ARRAY AND LINK ERROR CORRECTION IN A LOW POWER MEMORY SUB-SYSTEM
    1.
    发明申请
    MEMORY ARRAY AND LINK ERROR CORRECTION IN A LOW POWER MEMORY SUB-SYSTEM 审中-公开
    低功耗存储器子系统中的存储器阵列和链路错误校正

    公开(公告)号：US20170004035A1

    公开(公告)日：2017-01-05

    申请号：US14859063

    申请日：2015-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  David Ian WEST

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52

    Abstract: A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

    Abstract translation: 在低功率存储器子系统中的存储器阵列和链路纠错的方法包括在正常写入操作期间和在读取操作期间嵌入未使用的数据屏蔽位内的纠错码（ECC）奇偶校验位。 该方法还包括在掩模写入操作期间将ECC奇偶校验位嵌入对应于断言的数据屏蔽位的掩码写数据字节。

    DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE
    2.
    发明申请
    DYNAMIC CONTROL OF SIGNALING POWER BASED ON AN ERROR RATE 有权
    基于错误率的信号功率动态控制

    公开(公告)号：US20150332735A1

    公开(公告)日：2015-11-19

    申请号：US14280313

    申请日：2014-05-16

    Applicant: QUALCOMM Incorporated

    Inventor： Dexter Tamio CHUN ,  Vaishnav SRINIVAS ,  David Ian WEST ,  Deepti Vijayalakshmi SRIRAMAGIRI ,  Jungwon SUH ,  Jason THURSTON

    IPC: G11C5/14 ,  G06F11/07

    CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

    Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

    Abstract translation: 通过多相多路存储器总线通过片上系统（SoC）写入和读取动态随机存取存储器（DRAM）的功耗基于误码率（BER）和一个或多个阈值进行优化。 可以测量误码率（BER）并用于控制参数以实现功耗和精度之间的最佳平衡。 在正常任务模式操作与实时流量期间，执行误码率（BER）测量，有意添加抖动和检查阈值。 错误检测可以涵盖具有二进制数据块的每个存储器数据事务。

    DATA BANDWIDTH SCALABLE MEMORY SYSTEM
    3.
    发明申请
    DATA BANDWIDTH SCALABLE MEMORY SYSTEM 审中-公开
    数据带宽可调存储系统

    公开(公告)号：US20160291634A1

    公开(公告)日：2016-10-06

    申请号：US14677752

    申请日：2015-04-02

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  David Ian WEST ,  Dexter Tamio CHUN

    IPC: G06F1/14

    CPC classification number: G06F1/3253 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane.

    Abstract translation: 时钟被分配到处理器侧基本模式时钟收发器和存储器侧基本模式时钟收发器，将处理器和存储器之间的数据通道的相应端接口连接，以在数据通道上进行双向通信。 与双工通信同时，带宽模式在基带宽模式和放大模式之间切换。 放大模式可实现将时钟分配给处理器侧放大收发器和存储器侧放大收发器的放大时钟线，将处理器与处理器之间的放大数据通道的各个端点相连接 存储器，用于通过放大数据通道进行额外的双工通信。 基带宽模式禁用放大时钟线，禁止通过放大数据通道进行通信。

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