公开(公告)号：US20250119059A1

公开(公告)日：2025-04-10

申请号：US18481657

申请日：2023-10-05

Applicant: Qualcomm Incorporated

Inventor： Boris Dimitrov ANDREEV ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Yong XU ,  Satish KRISHNAMOORTHY

IPC: H02M3/04 ,  H04W52/02

Abstract: In some aspects, an electronic device may detect a start of a voltage ramp transition period associated with changing a voltage at which an integrated circuit operates from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage causes changes to one or more parameters that impact performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may trigger, responsive to detecting the start of the voltage ramp transition period, a dynamic calibration mode that compensates for the changes to the one or more parameters that impact the performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may exit the dynamic calibration mode responsive to detecting an end of the voltage ramp transition period. Numerous other aspects are described.

公开(公告)号：US20240161808A1

公开(公告)日：2024-05-16

申请号：US17988186

申请日：2022-11-16

Applicant: QUALCOMM Incorporated

Inventor： Yong XU ,  Boris Dimitrov ANDREEV ,  Yuxin LI ,  Vikas MAHENDIYAN

IPC: G11C11/4076 ,  H03K19/20 ,  H03L7/081

CPC classification number: G11C11/4076 ,  H03K19/20 ,  H03L7/0812

Abstract: In certain aspects, a system includes a first clock source configured to generate a first clock signal, a second clock source configured to generate a second clock signal, a clock path, and an OR gate having a first input, a second input, and an output, wherein the output of the OR gate is coupled to the clock path. The system also includes a first clock gating circuit coupled between the first clock source and the first input of the OR gate, and a second clock gating circuit coupled between the second clock source and the second input of the OR gate.

公开(公告)号：US20240105243A1

公开(公告)日：2024-03-28

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong XU ,  Satish KRISHNAMOORTHY ,  Boris Dimitrov ANDREEV ,  Patrick ISAKANIAN ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Ravindra Arvind KHEDKAR

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.