公开(公告)号：US11417622B2

公开(公告)日：2022-08-16

申请号：US17071432

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  John Holmes ,  Xuefeng Zhang ,  Dongming He

IPC: H01L23/00

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：US11721656B2

公开(公告)日：2023-08-08

申请号：US17409334

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Yujen Chen ,  Hung-Yuan Hsu ,  Dongming He

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05562 ,  H01L2224/1146 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13019 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16503

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.

公开(公告)号：US11437335B2

公开(公告)日：2022-09-06

申请号：US16921152

申请日：2020-07-06

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Aniket Patil ,  Bohan Yan ,  Dongming He

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/367

Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

公开(公告)号：US08963339B2

公开(公告)日：2015-02-24

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L21/98

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US20240096845A1

公开(公告)日：2024-03-21

申请号：US17934023

申请日：2022-09-21

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Yujen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/1712 ,  H01L2224/27416 ,  H01L2224/27614 ,  H01L2224/29191 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Circuit packages with a polymer layer around the bump interconnects have a reduced number of shorts between the bump interconnects and have reduced underfill delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects employed for passing logic signals, data signals, and/or power. The bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. The side surfaces of the bump interconnects extend in a direction from the second component to the first. The circuit package includes the polymer layer disposed on the surface of the first component around the bump interconnects and on the side surfaces of the bump interconnects. The polymer layer reduces shorts between the side surfaces of adjacent bump interconnects and reduces delamination of an underfill disposed between the first and second components.

公开(公告)号：US11694982B2

公开(公告)日：2023-07-04

申请号：US17185244

申请日：2021-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wei Hu ,  Dongming He ,  Wen Yin ,  Zhe Guan ,  Lily Zhao

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/11013 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/13147 ,  H01L2224/13584 ,  H01L2224/13655

Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar. The die interconnect may also include a low wetting layer formed on the wetting barrier.

公开(公告)号：US20210242160A1

公开(公告)日：2021-08-05

申请号：US16921152

申请日：2020-07-06

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon Kang ,  Aniket Patil ,  Bohan Yan ,  Dongming He

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/532

Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation. The dielectric layer in the package substrate may also include dielectric materials having different thermal conductivities to further facilitate thermal dissipation and/or desired electrical or mechanical characteristics.

公开(公告)号：US20140097535A1

公开(公告)日：2014-04-10

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM INCORPORATED

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/98 ,  H01L23/488

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US20240371736A1

公开(公告)日：2024-11-07

申请号：US18310331

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Dongming He ,  Ryan Lane ,  Kuiwon Kang ,  Lily Zhao

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

公开(公告)号：US11557557B2

公开(公告)日：2023-01-17

申请号：US16917295

申请日：2020-06-30

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Lily Zhao

IPC: H01L23/00

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.