Invention Application
- Patent Title: STACKED MULTI-CHIP INTEGRATED CIRCUIT PACKAGE
- Patent Title (中): 堆叠多芯片集成电路封装
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Application No.: US13647375Application Date: 2012-10-08
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Publication No.: US20140097535A1Publication Date: 2014-04-10
- Inventor: Dongming He , Zhongping Bao , Zhenyu Huang
- Applicant: QUALCOMM INCORPORATED
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM INCORPORATED
- Current Assignee: QUALCOMM INCORPORATED
- Current Assignee Address: US CA San Diego
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/538 ; H01L21/98 ; H01L23/488

Abstract:
A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.
Public/Granted literature
- US08963339B2 Stacked multi-chip integrated circuit package Public/Granted day:2015-02-24
Information query
IPC分类: