公开(公告)号：US08963339B2

公开(公告)日：2015-02-24

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L21/98

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US20140097535A1

公开(公告)日：2014-04-10

申请号：US13647375

申请日：2012-10-08

Applicant: QUALCOMM INCORPORATED

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/98 ,  H01L23/488

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。

公开(公告)号：US09406649B2

公开(公告)日：2016-08-02

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

公开(公告)号：US20150155265A1

公开(公告)日：2015-06-04

申请号：US14598053

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Dongming He ,  Zhongping Bao ,  Zhenyu Huang

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/3121 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package.

Abstract translation: 提供了一种多芯片集成电路（IC）封装，其被配置为防止由于翘曲而导致的故障。 IC封装可以包括衬底，一级IC芯片和多个二级IC芯片。 一级IC管芯具有电耦合到衬底的表面。 多个二级IC管芯堆叠在一级IC管芯上方。 多个二级IC管芯可以各自具有电耦合到衬底的有源表面。 多个二级IC管芯可以并排布置，使得多个二级IC管芯的有效表面基本上位于相同的平面中。 相对于单个管芯构造，二级IC管芯被分离，从而抑制由于IC封装翘曲引起的开裂，剥离和/或其它潜在故障。