公开(公告)号：US11417622B2

公开(公告)日：2022-08-16

申请号：US17071432

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  John Holmes ,  Xuefeng Zhang ,  Dongming He

IPC: H01L23/00

Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

公开(公告)号：US20170294422A1

公开(公告)日：2017-10-12

申请号：US15225910

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Michael James Solimando ,  William Stone ,  John Holmes ,  Christopher Healy ,  Rajendra Pendse ,  Sun Yun

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L21/54 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

公开(公告)号：US20240355747A1

公开(公告)日：2024-10-24

申请号：US18304195

申请日：2023-04-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  John Holmes ,  Aniket Patil ,  Bin Yang

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5383 ,  H01L21/481 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Substrate with multiple core layers to provide varied thickness cavities supporting varied thickness embedded electrical devices, and related integrated circuit (IC) packages and fabrication methods. To provide for core layer of the substrate to support multiple embedded electrical devices, multiple core layers are provided in the substrate. Providing multiple core layers in the substrate allows multiple cavities to be formed in the core layers at multiple depths to compatibly support embedding of multiple electrical devices of varied thicknesses in the core layers. Thus, providing multiple core layers in the substrate can compatibly support forming cavities of multiple thicknesses that are compatible with multiple electrical devices of different thicknesses to be embedded therein. In this manner, design parameters of the overall thickness of the core layer of a substrate can be independent of the variation in thicknesses of multiple embedded electrical devices desired to be embedded therein.

公开(公告)号：US10002857B2

公开(公告)日：2018-06-19

申请号：US15225910

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Michael James Solimando ,  William Stone ,  John Holmes ,  Christopher Healy ,  Rajendra Pendse ,  Sun Yun

IPC: H01L23/367 ,  H01L23/02 ,  H01L25/065 ,  H01L21/54 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L21/54 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.