公开(公告)号：US20240387429A1

公开(公告)日：2024-11-21

申请号：US18318691

申请日：2023-05-16

Applicant: QUALCOMM Incorporated

Inventor： Yujen Chen ,  Yangyang Sun ,  Wei Wang

IPC: H01L23/00

Abstract: Underfill and bump interconnects in a circuit package expand at different rates during a thermal reflow process, causing stress at one end of a bump interconnect that couples to a metal pad. A bump interconnect having multiple isolated areas of contact between a conductive pillar and the metal pad, rather than a single larger continuous contact area, distributes the concentration of stresses to reduce the peak stress, which reduces the chances of damage due to stress occurring between the metal pad and the conductive pillar or in a dielectric layer adjacent to the metal pad. In some examples, before formation of the conductive pillar, a passivation layer is disposed in a pattern on the metal pad with openings in which a plurality of surfaces of the second end of the conductive pillar contact the metal pad.

公开(公告)号：US20240096845A1

公开(公告)日：2024-03-21

申请号：US17934023

申请日：2022-09-21

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Dongming He ,  Yujen Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/73 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/1712 ,  H01L2224/27416 ,  H01L2224/27614 ,  H01L2224/29191 ,  H01L2224/3201 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/381 ,  H01L2924/3841

Abstract: Circuit packages with a polymer layer around the bump interconnects have a reduced number of shorts between the bump interconnects and have reduced underfill delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects employed for passing logic signals, data signals, and/or power. The bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. The side surfaces of the bump interconnects extend in a direction from the second component to the first. The circuit package includes the polymer layer disposed on the surface of the first component around the bump interconnects and on the side surfaces of the bump interconnects. The polymer layer reduces shorts between the side surfaces of adjacent bump interconnects and reduces delamination of an underfill disposed between the first and second components.

公开(公告)号：US11721656B2

公开(公告)日：2023-08-08

申请号：US17409334

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Yujen Chen ,  Hung-Yuan Hsu ,  Dongming He

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/16 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05562 ,  H01L2224/1146 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13019 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/16225 ,  H01L2224/16503

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.