公开(公告)号：US20230422525A1

公开(公告)日：2023-12-28

申请号：US18203666

申请日：2023-05-31

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Wen-Chin Tsai ,  Isabella Song ,  Che-Hung Kuo ,  Hsing-Chih Liu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Wen-Sung Hsu

IPC: H10B80/00 ,  H01L23/538 ,  H01L23/31 ,  H10B12/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L23/5383 ,  H01L23/3128 ,  H10B12/00 ,  H01L23/562 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L24/16

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.

公开(公告)号：US20230282625A1

公开(公告)日：2023-09-07

申请号：US18107520

申请日：2023-02-09

Applicant: MEDIATEK INC.

Inventor： Ta-Jen Yu ,  Shih-Chin Lin ,  Tai-Yu Chen ,  Bo-Jiun Yang ,  Bing-Yeh Lin ,  Yung-Cheng Huang ,  Wen-Sung Hsu ,  Bo-Hao Ma ,  Isabella Song

IPC: H01L25/10 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/481 ,  H01L23/49866 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/48 ,  H01L2224/73204 ,  H01L2224/08112 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/183

Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.

公开(公告)号：US09908203B2

公开(公告)日：2018-03-06

申请号：US15420140

申请日：2017-01-31

Applicant: MEDIATEK Inc.

Inventor： Tao Cheng ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L25/10 ,  B23K35/02 ,  H01L23/498 ,  B23K35/26 ,  B23K101/40

CPC classification number: B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  B23K35/264 ,  B23K35/30 ,  B23K2101/40 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13561 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A semiconductor package includes a first substrate, a second substrate, a composite solder ball and a first semiconductor component. The composite solder ball includes a core, an encapsulating layer and a barrier layer. The composite solder ball is disposed between the first substrate and the second substrate for electrically connecting the first substrate and the second substrate. The barrier layer is disposed between the core and the encapsulating layer. Wherein a melting point of the barrier layer is higher than a melting point of the core, the melting point of the core is higher than a melting point of the encapsulating layer. The first semiconductor component is disposed between the first substrate and the second substrate.

公开(公告)号：US09184107B2

公开(公告)日：2015-11-10

申请号：US14585575

申请日：2014-12-30

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/373 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球，其中第一横截面尺寸和第二横截面尺寸之间的比率为约1：2-1：6。

公开(公告)号：US10242927B2

公开(公告)日：2019-03-26

申请号：US15342138

申请日：2016-11-03

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Ming-Jen Hsiung

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the substrate and has an upper surface. The film is disposed on the upper surface of the first electronic component. The package body encapsulates the first electronic component and the film.

公开(公告)号：US10186488B2

公开(公告)日：2019-01-22

申请号：US15672440

申请日：2017-08-09

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/50

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

公开(公告)号：US10121222B2

公开(公告)日：2018-11-06

申请号：US15242478

申请日：2016-08-19

Applicant: MediaTek Inc.

Inventor： Ying-Chieh Chen ,  I-Hsuan Lu ,  Shih-Chin Lin

IPC: G06T1/60 ,  G06T11/60

Abstract: A graphics processing unit (GPU) renders graphical objects into a group of pixels and stores the pixels in an on-chip buffer on the same chip as the GPU. Each pixel has an alpha value that indicates transparency of the pixel. The GPU reads the alpha value of each pixel from the on-chip buffer. According to alpha values of the group of pixels, the GPU generates an alpha hint in the system memory for the group of pixels. The alpha hint represents an aggregate of the alpha values of the group of pixels. The GPU then stores the group of pixels into a frame buffer in the system memory.

公开(公告)号：US09361697B1

公开(公告)日：2016-06-07

申请号：US14582134

申请日：2014-12-23

Applicant: MediaTek Inc.

Inventor： Ming-Hao Liao ,  Chih-Ching Chen ,  Shih-Chin Lin ,  Hung-Wei Wu

IPC: G06T15/50 ,  G06T7/00 ,  G06T7/40 ,  G06T1/20 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/40

Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.

Abstract translation: 提供了具有binning渲染和相关的预深度处理方法的图形处理电路。 首先，接收对应于指定瓦片的第一原语的第一深度数据。 然后，从预Z缓冲器读取对应于指定瓦片的预深度数据。 如果第一深度数据不大于预深度数据，并且第一原语是不透明原语，则用第一深度数据更新预深度数据。 如果第一深度数据不大于预深度数据，并且第一图元是半透明图元，则根据第一深度数据和预深度数据来定义不确定性排序范围，并且更新预深度数据 具有不确定性排序范围。

公开(公告)号：US12118653B2

公开(公告)日：2024-10-15

申请号：US17944415

申请日：2022-09-14

Applicant: MediaTek Inc.

Inventor： Po-Yu Huang ,  Shih-Chin Lin ,  Jen-Jung Cheng ,  Tu-Hsiu Lee

IPC: G06T15/00 ,  G06T1/20 ,  G06T7/50

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T7/50

Abstract: A system, method, and computer program product are provided for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

公开(公告)号：US12021068B2

公开(公告)日：2024-06-25

申请号：US17492693

申请日：2021-10-04

Applicant: MEDIATEK INC.

Inventor： Bo-Jiun Yang ,  Wen-Sung Hsu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Kun-Ting Hung

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor device includes a bottom package, a top package stacked on the bottom package, and an interposer disposed between the bottom package and the top package. The top package is electrically connected to the interposer through a plurality of peripheral solder balls. At least a dummy thermal feature is disposed on the interposer and surrounded by the plurality of peripheral solder balls.