公开(公告)号：US20170084541A1

公开(公告)日：2017-03-23

申请号：US15162760

申请日：2016-05-24

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive layer, a first pillar layer, a first package body and a second conductive layer, wherein the first pillar layer is formed on the first conductive layer, the first package body encapsulates the first conductive layer and the first pillar layer, and the second conductive layer electrically connects to the first pillar layer. The first electronic component is disposed above the second conductive layer of the package substrate. The second package body encapsulates the first electronic component and the second conductive layer.

公开(公告)号：US08859340B2

公开(公告)日：2014-10-14

申请号：US14154564

申请日：2014-01-14

Applicant: MediaTek Inc.

Inventor： Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/52 ,  H01L23/498 ,  H01L21/56 ,  H01L25/065 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method includes the operations performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet; mounting a carrier on the top surface of the metal sheet, covering the first recesses; performing a second anisotropic etching process to remove a portion of the metal sheet under the first recesses from the bottom surface of the metal sheet; filling a molding material from the bottom surface of the metal sheet, leaving the bottom surface of the metal sheet exposed; forming a passivation layer on the top surface of the metal sheet, having a plurality of openings therethrough; forming a plurality of first metal vias through the opening; and forming a solder mask layer on the passivation layer, leaving the first metal vias exposed.

Abstract translation: 一种方法包括执行第一各向异性蚀刻工艺以从金属片的顶表面去除金属片的一部分的操作，从而在金属片中形成多个第一凹槽; 将载体安装在金属板的顶表面上，覆盖第一凹槽; 执行第二各向异性蚀刻工艺以从所述金属片的底表面去除所述第一凹部下方的所述金属片的一部分; 从金属板的底面填充成型材料，使金属板的底面露出; 在所述金属板的顶表面上形成钝化层，具有穿过其中的多个开口; 通过所述开口形成多个第一金属通孔; 并在钝化层上形成焊接掩模层，使第一金属通孔露出。

公开(公告)号：US10354974B2

公开(公告)日：2019-07-16

申请号：US14736684

申请日：2015-06-11

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Andrew C. Chang ,  Tao Cheng

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/528 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

公开(公告)号：US20170338183A1

公开(公告)日：2017-11-23

申请号：US15672440

申请日：2017-08-09

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/81005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

公开(公告)号：US09040359B2

公开(公告)日：2015-05-26

申请号：US14482112

申请日：2014-09-10

Applicant: MediaTek Inc.

Inventor： Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

IPC: H01L21/00 ,  H01L21/4763 ,  H01L27/08 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.

Abstract translation: 一种用于制造模制插入件封装的方法包括进行第一各向异性蚀刻工艺以从金属板的顶表面去除金属片的一部分，从而在金属片中形成多个第一凹槽，形成覆盖金属片的成型材料 顶表面，填充第一凹槽，在模制材料中形成多个第一通孔，其中第一通孔开口暴露顶表面，在第一通孔中形成多个第一金属通孔，以及多个第一再分配层图案 分别在第一金属通孔上，进行第二各向异性蚀刻工艺以从金属板的底表面去除金属片的一部分，直到模制材料的底部暴露，并且在模制材料上形成焊接掩模层， 留下第一个重分布层图案。

公开(公告)号：US10573615B2

公开(公告)日：2020-02-25

申请号：US14173976

申请日：2014-02-06

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US11469201B2

公开(公告)日：2022-10-11

申请号：US16721475

申请日：2019-12-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US10573616B2

公开(公告)日：2020-02-25

申请号：US15194658

申请日：2016-06-28

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US10186488B2

公开(公告)日：2019-01-22

申请号：US15672440

申请日：2017-08-09

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung Hsu ,  Shih-Chin Lin ,  Tao Cheng ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L25/065 ,  H01L25/16 ,  H01L23/498 ,  H01L23/50

Abstract: A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first electronic component is disposed above the second conductive layer of the package substrate. Then, a second package body encapsulating the first electronic component and the second conductive layer is formed. Then, the carrier is carried. Wherein in the step of forming the package substrate includes a step of forming a first conductive layer on the carrier, a step of forming a first pillar layer on the first conductive layer, a step of forming a first package body encapsulating the first conductive layer and the first pillar layer and a step of forming a second conductive layer on the first pillar layer.

公开(公告)号：US09177899B2

公开(公告)日：2015-11-03

申请号：US13721983

申请日：2012-12-20

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L21/48 ,  H01L21/77 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/49541 ,  H01L21/48 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L28/00 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/12042 ,  Y10T29/41 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract translation: 本发明提供半导体封装和用于制造用于半导体封装的基座的方法。 半导体封装包括嵌入基座中的导电迹线。 半导体器件通过导电结构安装在导电迹线上。