公开(公告)号：US10418480B2

公开(公告)日：2019-09-17

申请号：US15426414

申请日：2017-02-07

Applicant: MEDIATEK INC.

Inventor： Chu-Wei Hu ,  Cheng Hua Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device capable of high-voltage operation includes a semiconductor substrate having a first conductivity type. A first well doped region is formed in the semiconductor substrate, having a second conductivity type that is the opposite of the first conductivity type. A first doped region and a second doped region are formed on the first well doped region, having the second conductivity type. A first gate structure is formed over the first well doped region and adjacent to the first doped region. A second gate structure overlaps the first gate structure and the first well doped region. A third gate structure is formed beside the second gate structure and close to the second doped region. The top surface of the first well doped region between the second gate structure and the third gate structure avoids having any gate structure and silicide formed thereon.

公开(公告)号：US11728320B2

公开(公告)日：2023-08-15

申请号：US17726595

申请日：2022-04-22

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu Lu ,  Chu-Wei Hu ,  Hsin-Hsin Hsiao

IPC: H01L25/16 ,  H01L23/538

CPC classification number: H01L25/162 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

公开(公告)号：US11342316B2

公开(公告)日：2022-05-24

申请号：US17005528

申请日：2020-08-28

Applicant: MEDIATEK Inc.

Inventor： Tien-Yu Lu ,  Chu-Wei Hu ,  Hsin-Hsin Hsiao

IPC: H05K7/00 ,  H01L25/16 ,  H01L23/538

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

公开(公告)号：US09508786B2

公开(公告)日：2016-11-29

申请号：US14886221

申请日：2015-10-19

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: A method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US20230260894A1

公开(公告)日：2023-08-17

申请号：US18097296

申请日：2023-01-16

Applicant: MEDIATEK INC.

Inventor： Chu-Wei Hu ,  Chien-Kai Huang ,  Tien-Yu Lu

IPC: H01L23/522 ,  H01L23/00 ,  H10B80/00 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L24/08 ,  H10B80/00 ,  H01L24/09 ,  H01L24/05 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L23/49833 ,  H01L23/49816 ,  H01L23/5286 ,  H01L2224/08145 ,  H01L2924/1443 ,  H01L2924/1433 ,  H01L2224/09515 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/1438 ,  H01L2924/1441

Abstract: A semiconductor device includes an application processor (AP) die and a memory die directly bonded to the AP die. The memory die includes a substrate, a non-volatile memory structure on the substrate, and at least one trench capacitor in the substrate.

公开(公告)号：US09379175B2

公开(公告)日：2016-06-28

申请号：US14557743

申请日：2014-12-02

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/266 ,  H01L29/167 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. Furthermore, a method of fabricating an integrated circuit is also provided. The method includes forming a first polysilicon region having an initial grain size on a substrate. The first polysilicon region is implanted with a first dopant of a first conductivity type and a second dopant. After the implantation, the first polysilicon region has a first grain size larger than the initial grain size. Then, a laser rapid thermal annealing process is performed to the first polysilicon region.

Abstract translation: 集成电路包括在基板上形成的具有第一晶粒尺寸的第一多晶硅区域。 集成电路还包括形成在基板上的具有与第一晶粒尺寸不同的第二晶粒尺寸的第二多晶硅区域。 此外，还提供了一种制造集成电路的方法。 该方法包括在衬底上形成具有初始晶粒尺寸的第一多晶硅区域。 第一多晶硅区域注入第一导电类型的第一掺杂剂和第二掺杂剂。 在注入之后，第一多晶硅区域具有比初始晶粒尺寸大的第一晶粒尺寸。 然后，对第一多晶硅区域进行激光快速热退火处理。

公开(公告)号：US09793337B2

公开(公告)日：2017-10-17

申请号：US15167783

申请日：2016-05-27

Applicant: MediaTek Inc.

Inventor： Yuan-Fu Chung ,  Chu-Wei Hu ,  Yuan-Hung Chung

IPC: H01L21/70 ,  H01L49/02 ,  H01L21/265 ,  H01L21/268 ,  H01L21/28 ,  H01L21/324 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L21/02 ,  H01L21/266 ,  H01L29/167 ,  H01L21/3215 ,  H01L27/02

CPC classification number: H01L28/20 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/8234 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/167 ,  H01L29/4916

Abstract: An integrated circuit includes a first polysilicon region having a first grain size formed on a substrate. The integrated circuit also includes a second polysilicon region, having a second grain size different from the first grain size, formed on the substrate. The first polysilicon region is doped with a first dopant of a first conductive type and a second dopant selected from elements of group IIIA and group IVA which has an atomic weight heavier than that of silicon.