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公开(公告)号：US20230153198A1
公开(公告)日：2023-05-18
申请号：US17528346
申请日：2021-11-17
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Huang , Yung-Chun Li
CPC classification number: G06F11/1016 , G06F3/0655 , G06F3/0625 , G06F3/0679 , G06F2201/805
Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.
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公开(公告)号：US20160147464A1
公开(公告)日：2016-05-26
申请号：US14805498
申请日：2015-07-22
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06
CPC classification number: G06F12/00 , G06F12/0246 , G06F2212/7202 , G06F2212/7209 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.
Abstract translation: 一种用于存储器的操作方法，所述存储器包括至少一个存储块，所述至少一个存储块包括与所述第一页对应的多个第一页和多个第二页，所述操作方法包括以下步骤：确定所述第一页的目标第一页 页面是有效的，其中目标第一页面对应于第二页面的目标第二页面; 如果目标第一页有效，则在目标第二页上执行第一类型编程; 如果目标第一页无效，则在目标第二页上执行第二类型编程。
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公开(公告)号：US11966628B2
公开(公告)日：2024-04-23
申请号：US17830471
申请日：2022-06-02
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Wei-Chen Wang , Han-Wen Hu , Yung-Chun Li , Huai-Mu Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
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公开(公告)号：US11914887B2
公开(公告)日：2024-02-27
申请号：US17403927
申请日：2021-08-17
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Han-Wen Hu , Bo-Rong Lin , Huai-Mu Wang
CPC classification number: G06F3/0655 , G06F3/0619 , G06F3/0679 , G06F11/1072 , G06F12/0246
Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.
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公开(公告)号：US10445008B2
公开(公告)日：2019-10-15
申请号：US15705309
申请日：2017-09-15
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yung-Chun Li , Ping-Hsien Lin , Yu-Ming Chang
Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.
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Patent Agency Ranking
公开(公告)号：US09558108B2
公开(公告)日：2017-01-31
申请号：US14018149
申请日：2013-09-04
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Hsing-Chen Lu , Hsiang-Pang Li , Cheng-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F12/0246 , G06F2212/7205 , G11C16/0483 , G11C16/16 , G11C16/3427
Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.
Abstract translation: 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。
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公开(公告)号：US09305638B1
公开(公告)日：2016-04-05
申请号：US14526560
申请日：2014-10-29
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Ming Chang , Yung-Chun Li , Chih-Chang Hsieh , Shih-Fu Huang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
Abstract translation: 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。
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公开(公告)号：US12169702B2
公开(公告)日：2024-12-17
申请号：US17411938
申请日：2021-08-25
Applicant: MACRONIX International Co., Ltd.
Inventor： Bo-Rong Lin , Yung-Chun Li , Han-Wen Hu , Huai-Mu Wang
Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.
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公开(公告)号：US11663074B1
公开(公告)日：2023-05-30
申请号：US17528346
申请日：2021-11-17
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Ming Huang , Yung-Chun Li
CPC classification number: G06F11/1016 , G06F3/0625 , G06F3/0655 , G06F3/0679 , G06F2201/805
Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.
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公开(公告)号：US20230161556A1
公开(公告)日：2023-05-25
申请号：US17701725
申请日：2022-03-23
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang , Wei-Chen Wang
IPC: G06F7/544 , G06F7/527 , G06F7/72 , G06F12/0882 , G06F13/16
CPC classification number: G06F7/5443 , G06F7/5272 , G06F7/729 , G06F12/0882 , G06F13/1673
Abstract: A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.
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