公开(公告)号：US11809838B2

公开(公告)日：2023-11-07

申请号：US17365034

申请日：2021-07-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen Hu ,  Yung-Chun Lee ,  Bo-Rong Lin ,  Huai-Mu Wang

IPC: G06F7/544 ,  G11C7/06

CPC classification number: G06F7/5443 ,  G11C7/06

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit coupled to the memory array, for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results; a counting unit coupled to the multiplication circuit, for performing bitwise counting on the multiplication results to generate a MAC (multiplication and accumulation) operation result.

公开(公告)号：US11656988B2

公开(公告)日：2023-05-23

申请号：US17542557

申请日：2021-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen Hu ,  Yung-Chun Li ,  Bo-Rong Lin ,  Huai-Mu Wang

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1024

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.

公开(公告)号：US20220075601A1

公开(公告)日：2022-03-10

申请号：US17411938

申请日：2021-08-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Bo-Rong Lin ,  Yung-Chun Li ,  Han-Wen Hu ,  Huai-Mu Wang

IPC: G06F7/544 ,  G06F7/74 ,  G11C7/06 ,  G11C7/10

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

公开(公告)号：US12169702B2

公开(公告)日：2024-12-17

申请号：US17411938

申请日：2021-08-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Bo-Rong Lin ,  Yung-Chun Li ,  Han-Wen Hu ,  Huai-Mu Wang

IPC: G06F7/544 ,  G06G7/16 ,  G11C7/06 ,  G11C7/10

Abstract: An in-memory computing method and an in-memory computing apparatus are adapted to perform multiply-accumulate (MAC) operations on a memory by a processor. In the method, a pre-processing operation is respectively performed on input data and weight data to be written into input lines and memory cells of the memory to divide the input data and weight data into a primary portion and a secondary portion. The input data and the weight data divided into the primary portion and the secondary portion are written into the input lines and the memory cells in batches to perform the MAC operations and obtain a plurality of computation results. According to a numeric value of each of the computation results, the computation results are filtered. According to the portions to which the computation results correspond, a post-processing operation is performed on the filtered computation results to obtain output data.

公开(公告)号：US20230161556A1

公开(公告)日：2023-05-25

申请号：US17701725

申请日：2022-03-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen Hu ,  Yung-Chun Li ,  Bo-Rong Lin ,  Huai-Mu Wang ,  Wei-Chen Wang

IPC: G06F7/544 ,  G06F7/527 ,  G06F7/72 ,  G06F12/0882 ,  G06F13/16

CPC classification number: G06F7/5443 ,  G06F7/5272 ,  G06F7/729 ,  G06F12/0882 ,  G06F13/1673

Abstract: A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.

公开(公告)号：US12106070B2

公开(公告)日：2024-10-01

申请号：US17375024

申请日：2021-07-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen Hu ,  Yung-Chun Lee ,  Bo-Rong Lin ,  Huai-Mu Wang

IPC: G06J1/00 ,  G06F7/544

CPC classification number: G06F7/5443 ,  G06J1/00 ,  Y02D10/00

Abstract: A memory device and an operation method thereof are provided. The memory device includes: a memory array including a plurality of memory cells for storing a plurality of weights; a multiplication circuit for performing bitwise multiplication on a plurality of input data and the weights to generate a plurality of multiplication results, wherein in performing bitwise multiplication, the memory cells generate a plurality of memory cell currents; a digital accumulating circuit for performing a digital accumulating on the multiplication results; an analog accumulating circuit for performing an analog accumulating on the memory cell currents to generate a first MAC operation result; and a decision unit for deciding whether to perform the analog accumulating, the digital accumulating or a hybrid accumulating, wherein in performing the hybrid accumulating, whether the digital accumulating circuit is triggered is based on the first MAC operation result.

公开(公告)号：US11966628B2

公开(公告)日：2024-04-23

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Wang ,  Han-Wen Hu ,  Yung-Chun Li ,  Huai-Mu Wang ,  Chien-Chung Ho ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US11914887B2

公开(公告)日：2024-02-27

申请号：US17403927

申请日：2021-08-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun Li ,  Han-Wen Hu ,  Bo-Rong Lin ,  Huai-Mu Wang

IPC: G06F3/06 ,  G06F11/10 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/1072 ,  G06F12/0246

Abstract: A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.