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公开(公告)号：US20230161556A1
公开(公告)日：2023-05-25
申请号：US17701725
申请日：2022-03-23
发明人： Han-Wen Hu , Yung-Chun Li , Bo-Rong Lin , Huai-Mu Wang , Wei-Chen Wang
IPC分类号： G06F7/544 , G06F7/527 , G06F7/72 , G06F12/0882 , G06F13/16
CPC分类号： G06F7/5443 , G06F7/5272 , G06F7/729 , G06F12/0882 , G06F13/1673
摘要： A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.
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公开(公告)号：US11550709B2
公开(公告)日：2023-01-10
申请号：US16655510
申请日：2019-10-17
发明人： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
摘要： A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.
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公开(公告)号：US20210326114A1
公开(公告)日：2021-10-21
申请号：US17217482
申请日：2021-03-30
发明人： Wei-Chen Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
摘要： An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.
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公开(公告)号：US11966628B2
公开(公告)日：2024-04-23
申请号：US17830471
申请日：2022-06-02
发明人： Wei-Chen Wang , Han-Wen Hu , Yung-Chun Li , Huai-Mu Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0673
摘要： A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.
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5.发明授权公开(公告)号：US11194515B2
公开(公告)日：2021-12-07
申请号：US16571249
申请日：2019-09-16
发明人： Ping-Hsien Lin , Wei-Chen Wang , Hsiang-Pang Li , Shu-Hsien Liao , Che-Wei Tsao , Yuan-Hao Chang , Tei-Wei Kuo
摘要： The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.
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公开(公告)号：US20200319803A1
公开(公告)日：2020-10-08
申请号：US16742811
申请日：2020-01-14
发明人： Wei-Chen Wang , Ping-Hsien Lin , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06 , G06F16/901 , G06F12/10
摘要： A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.
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公开(公告)号：US12050888B2
公开(公告)日：2024-07-30
申请号：US17217482
申请日：2021-03-30
发明人： Wei-Chen Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G06F7/5443 , G06F7/768 , G06N3/04 , G06N3/08 , G11C13/004 , H03M7/04 , H03M7/24
摘要： An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.
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公开(公告)号：US11640255B2
公开(公告)日：2023-05-02
申请号：US17518624
申请日：2021-11-04
发明人： Wei-Chen Wang , Ting-Hsuan Lo , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
摘要： Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.
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公开(公告)号：US11526285B2
公开(公告)日：2022-12-13
申请号：US16564066
申请日：2019-09-09
发明人： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
摘要： A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.
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公开(公告)号：US12056361B2
公开(公告)日：2024-08-06
申请号：US17814888
申请日：2022-07-26
发明人： Wei-Chen Wang , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G06F3/0613 , G06F3/0644 , G06F3/0679
摘要： An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.
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