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公开(公告)号：US12050888B2
公开(公告)日：2024-07-30
申请号：US17217482
申请日：2021-03-30
Applicant: MACRONIX International Co., Ltd.
Inventor： Wei-Chen Wang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
CPC classification number: G06F7/5443 , G06F7/768 , G06N3/04 , G06N3/08 , G11C13/004 , H03M7/04 , H03M7/24
Abstract: An in-memory computing method and apparatus, adapted for a processor to perform MAC operations on a memory, are provided. In the method, a format of binary data of weights is transformed from a floating-point format into a quantized format by truncating at least a portion of fraction bits of the binary data and calculating complements of remaining bits, and programming the transformed binary data into cells of the memory. A tuning procedure is performed by iteratively inputting binary data of input signals into the memory, integrating outputs of the memory, and adjusting the weights programmed to the cells based on the integrated outputs. The binary data of the weights is reshaped based on a probability of reducing bits with a value of one in the binary data of each weight. The tuning procedure is repeated until an end condition is met.
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公开(公告)号：US09966970B2
公开(公告)日：2018-05-08
申请号：US14682244
申请日：2015-04-09
Applicant: Oracle International Corporation
Inventor： Sadar Ahmed
Abstract: A method for determining a mapping between two code spaces is disclosed. The method may include receiving first and second plurality of data words. The least-significant-bits (LSBs) of a first data word of a first subset of the first plurality of data words may be compared to the LSBs of each data word of a second subset of the second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.
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公开(公告)号：US08570195B2
公开(公告)日：2013-10-29
申请号：US13077285
申请日：2011-03-31
Applicant: Rudi Baumgartl , Nikolaus Demharter , Roland Werner
Inventor： Rudi Baumgartl , Nikolaus Demharter , Roland Werner
IPC: H03M7/04
Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.
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4.发明授权公开(公告)号：US07667629B2
公开(公告)日：2010-02-23
申请号：US12127179
申请日：2008-05-27
Applicant: Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
Inventor： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC: H03M7/04
CPC classification number: H03M7/16
Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
Abstract translation: 使用虚拟空间生成奇数长度序列的灰度计数的方法。 可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。 这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。
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公开(公告)号：US06940430B1
公开(公告)日：2005-09-06
申请号：US11031632
申请日：2005-01-06
Applicant: Zining Wu
Inventor： Zining Wu
CPC classification number: H03M7/16
Abstract: In general, in one aspect, the invention features a Gray code decoder for decoding input numbers according to a K-bit Gray code and a Gray code encoder for encoding input numbers according to the K-bit Gray code. The K-bit Gray code is constructed from a M-bit Gray code having a one-bit separation I and a two-bit separation J and a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M≧N, and at least one of I and J is greater than, or equal to, 2N.
Abstract translation: 通常，在一个方面，本发明的特征在于一种格雷码解码器，用于根据K位格雷码解码输入号码，格格码编码器根据K位格雷码对输入号进行编码。 K位格雷码由具有一比特间隔I和两比特间隔J的M位格雷码构成，N位格雷码由N位格雷码组成，其中K = M + N，M> = N，I和J中的至少一个大于或等于2 N。
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Patent Agency Ranking
公开(公告)号：US20050010622A1
公开(公告)日：2005-01-13
申请号：US10616646
申请日：2003-07-10
Applicant: Peng-Hua Wang
Inventor： Peng-Hua Wang
CPC classification number: H03M7/04
Abstract: The method and apparatus use two inequalities to determine whether an estimated value obtained from conventional method and a correct value obtained from ideal conversion is identical. When those values are the same, the estimated value is not corrected; otherwise, according to the difference between those values, one is added or subtracted from the estimated value to obtain the correct result.
Abstract translation: 该方法和装置使用两个不等式来确定从常规方法获得的估计值和从理想转换获得的正确值是否相同。 当这些值相同时，估计值不能更正; 否则，根据这些值之间的差异，从估计值中增加或减去一个值以获得正确的结果。
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公开(公告)号：US5737142A
公开(公告)日：1998-04-07
申请号：US414690
申请日：1995-03-31
Applicant: Christopher P. Zook
Inventor： Christopher P. Zook
CPC classification number: G11B20/10175 , G11B20/10009 , G11B27/3027 , G11B5/5526 , G11B5/59633
Abstract: A rate 5/7, d=0 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a PR4 sliding threshold Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=0 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. Detecting the servo data with a PR4 Viterbi sequence detector, which is already provided in a read channel for detecting user data, increases the data density of the storage system. The cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.
Abstract translation: 速率5/7，d = 0信道码将格雷码伺服轨道地址编码到记录在磁盘上的通道数据; PR4滑动阈值维特比序列检测器在回读时检测记录的伺服轨迹地址; 成本有效的d = 0解码器将记录的伺服轨迹地址解码为其格雷码表示; 并且1/1 + D滤波器将格雷码轨迹地址解码为其二进制表示。 使用已经在用于检测用户数据的读通道中提供的PR4维特比序列检测器来检测伺服数据，增加了存储系统的数据密度。 通过在五位的部分中对格雷码轨道地址进行编码/解码来降低解码器的成本和复杂性。
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公开(公告)号：US5606318A
公开(公告)日：1997-02-25
申请号：US316317
申请日：1994-09-30
Applicant: Alan S. Feldman
Inventor： Alan S. Feldman
Abstract: An apparatus converts m-bit digital data having a scale factor of K.sub.1 to n-bit digital data having a scale factor of K.sub.2. The apparatus comprises a digital to analog converter which receives the m-bit digital data, for outputting a first analog signal representative of a value associated with the m-bit digital data. An amplifier receives the first analog signal multiplies it by a factor, and outputs a second analog signal. The factor of the amplifier is K.sub.2 /K.sub.1, such that the second analog signal has a value with the scale factor of K.sub.2 associated therewith. An analog to digital converter receives the second analog signal, and converts the second analog signal to the n-bit digital data. The n-bit digital data has the scale factor of K.sub.2 associated therewith, the value representative of the n-bit digital data being essentially equal in the example of the present application to the value representative of the m-bit digital data, however, this is not always a requirement.
Abstract translation: 一种装置将具有比例因子K1的m位数字数据转换成具有比例因子K2的n位数字数据。 该装置包括数模转换器，其接收m位数字数据，用于输出表示与m位数字数据相关联的值的第一模拟信号。 放大器接收第一模拟信号乘以因子，并输出第二模拟信号。 放大器的因素是K2 / K1，使得第二模拟信号具有与其相关联的比例因子为K2的值。 模数转换器接收第二模拟信号，并将第二模拟信号转换成n位数字数据。 n位数字数据具有与之相关联的K2的比例因子，表示本应用的示例中的n位数字数据的值基本上相等于表示m位数字数据的值的值，然而，这 并不总是要求。
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公开(公告)号：US4554529A
公开(公告)日：1985-11-19
申请号：US437129
申请日：1982-10-28
Applicant: Yoshiaki Moriyama , Kenji Yamagata
Inventor： Yoshiaki Moriyama , Kenji Yamagata
IPC: H03M5/04 , G11B5/09 , G11B20/14 , H03K5/156 , H03M7/04 , H03M7/14 , H04L25/48 , H04L25/49 , H03K13/00
CPC classification number: G11B20/1426 , H04L25/4906 , H04L25/4908
Abstract: In order to obtain sufficiently long values of T.sub.min and T.sub.w data conversion, and to reduce the dc or the low frequency component, a method for converting a binary data train comprises a first step for dividing the binary data train into a plurality of successive blocks each having M (M being a natural number) bit data, a second step for converting the M bit data into N (N being a natural number, and where N.gtoreq.M+1), and a third step for converting the N bit data in every L (L being a natural number) blocks into J (J being a natural number) bit data.
Abstract translation: 为了获得足够长的Tmin和Tw数据转换值，并且为了减小直流或低频分量，用于转换二进制数据串的方法包括第一步骤，用于将二进制数据序列分成多个连续的块 具有M（M是自然数）比特数据的第二步骤，用于将M比特数据转换为N（N是自然数，并且其中N> / = M + 1）的第二步骤，以及用于将N比特 每个L（L是自然数）的数据块成J（J为自然数）位数据。
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公开(公告)号：US3963098A
公开(公告)日：1976-06-15
申请号：US467698
申请日：1974-05-07
Applicant: Arthur M. Lewis , Charles L. Winkler
Inventor： Arthur M. Lewis , Charles L. Winkler
CPC classification number: B66B1/3492
Abstract: Position measurement apparatus which utilizes a digital code to accurately determine the position of a movable body along a travel path. The digital code is selected to provide, for any N consecutive bits of the code, a bit pattern which is unique. Indicia defining the code, and a reader, are arranged for relative motion in synchronism with movement of the movable body. Translating apparatus converts each combination of N consecutive bits read by the reader into an address defining the location of the movable body relative to the travel path. In a preferred embodiment, the digital code is a maximum length digital code, which is conveniently generated by a polynomial generator. The bit length of the code, which is equal to 2.sup.N -1, is selected according to the length of the travel path and the desired resolution.
Abstract translation: 位置测量装置利用数字代码精确地确定可移动体沿着行进路径的位置。 选择数字代码以对代码的任何N个连续位提供唯一的位模式。 定义代码的标记和读取器被布置成与可移动体的运动同步地进行相对运动。 翻译装置将由读取器读取的N个连续位的每个组合转换成限定可移动体相对于行进路径的位置的地址。 在优选实施例中，数字代码是最大长度数字代码，其被方便地由多项式生成器生成。 根据行进路径的长度和期望的分辨率来选择等于2N -1的码的位长度。
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