公开(公告)号：US09929897B2

公开(公告)日：2018-03-27

申请号：US15091393

申请日：2016-04-05

Applicant: Juniper Networks, Inc.

Inventor： Reji Thomas ,  Punit Kumar Jaiswal ,  Pranavadatta Dn ,  Jithin Girish

IPC: H04L25/48 ,  H04L12/24 ,  H04L12/741 ,  H04L29/08 ,  H04L12/707 ,  H04L12/703 ,  H04L12/26

CPC classification number: H04L41/0654 ,  H04L41/0213 ,  H04L43/0811 ,  H04L45/026 ,  H04L45/22 ,  H04L45/24 ,  H04L45/28 ,  H04L45/74 ,  H04L69/324

Abstract: The problem of being unable to run microBFD using an IPv6 address over any member links of a layer 2 LAG when the LAG is DOWN (and its IPv6 address becomes or is TENTATIVE), is solved by running DAD for the address configured for the microBFD once the individual link is in DISTRIBUTING or STANDBY state and triggering (or starting) microBFD once the DAD for that address completes successfully. Further, member links of the LAG may be permitted to continue running microBFD even if the LAG interface is DOWN and even if some other member links (but not all member links) of the LAG are DOWN.

公开(公告)号：US06873642B1

公开(公告)日：2005-03-29

申请号：US09830516

申请日：1999-10-13

Applicant: Wolfgang Fey ,  Ling Chen

Inventor： Wolfgang Fey ,  Ling Chen

IPC: B60T8/00 ,  H03M5/08 ,  H04L25/06 ,  H04L25/48 ,  H04L25/49 ,  H04L25/493 ,  H03D1/00

CPC classification number: H04L25/493 ,  H04L25/069

Abstract: The present invention relates to a method for conditioning a received signal that transmits coded data, wherein the coding of the data includes a defined coding clock pulse and the signal includes edges produced in accordance with the coding clock pulse, wherein from the received signal a time constant (tm) set in accordance with the coding clock pulse is determined, a first signal part which has a first edge is conditioned at a first time that is set in accordance with the time constant (tm) or in a first time window that is set in accordance with the time constant (tm), and a second signal part which has a second edge is conditioned at a second time that is set in accordance with the time constant (tm) and in dependence on the time of the first edge or in a second time window that is set in accordance with the time constant (tm) and in dependence on the time of the first edge.

Abstract translation: 本发明涉及一种用于调节发送编码数据的接收信号的方法，其中数据的编码包括定义的编码时钟脉冲，并且该信号包括根据编码时钟脉冲产生的边缘，其中从接收信号中的时间 确定根据编码时钟脉冲设定的常数（tm），具有第一边缘的第一信号部分在根据时间常数（tm）设置的第一时间被调节，或者在第一时间窗口 根据时间常数（tm）设置，并且具有第二边缘的第二信号部分在根据时间常数（tm）设置的第二时间和根据第一边缘的时间或 在根据时间常数（tm）设定的第二时间窗口中，并且依赖于第一边缘的时间。

公开(公告)号：US5999576A

公开(公告)日：1999-12-07

申请号：US891839

申请日：1997-07-14

Applicant: Chao-Cheng Lee

Inventor： Chao-Cheng Lee

IPC: H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  H04L25/48 ,  H03D3/22

CPC classification number: H03K5/133 ,  H03L7/0812 ,  H03K2005/00032

Abstract: A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.

Abstract translation: 延迟锁定环，其通过某些相同的延迟单元相位锁定晶体振荡的参考时钟，以产生某些精确的时间共享相位信号。 这些分时相位信号可用于恢复时钟/数据。 当与典型的锁相环比较时，本发明的优点是：（1）它可以容易地稳定; （2）相位误差不累积; （3）环路滤波器只需要一个电容器，减少了芯片的面积; （4）在多端口应用中不需要额外的环路滤波器，这进一步减小了芯片的面积。

公开(公告)号：US5905759A

公开(公告)日：1999-05-18

申请号：US691033

申请日：1996-08-07

Applicant: Takuya Ishida ,  Kanji Aoki

Inventor： Takuya Ishida ,  Kanji Aoki

IPC: H03K3/354 ,  H03B5/26 ,  H03M5/12 ,  H04L7/027 ,  H04L7/033 ,  H04L25/48 ,  H04L25/49 ,  H04L27/22 ,  H03D3/24

CPC classification number: H04L7/033 ,  H04L25/4904 ,  Y10S331/03

Abstract: A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.fs) in synchronism with an output of the edge detection means; a phase synchronization oscillation section synchronized in phase with the phase comparing timing signal for outputting a signal having a frequency n times the data transfer frequency fs; and a sampling section including means for generating the bit synchronization signal by dividing a frequency of a signal outputted from the phase synchronization oscillation means into 1/n, means for sampling the received data regenerating signal based on the bit synchronization signal and means for transforming sampled signal into a serial binary data.

Abstract translation: 本发明的数据解码电路可以通过使用诸如分相码和曼彻斯特码的代码从接收到的数据中再现位同步信号，其中可以通过中心区域的电压转换来检测二进制值 一个位单元，并将接收到的数据变换成一个串行二进制数据。 数据解码电路包括用于检测接收数据中的转变点的边缘检测部分; 脉冲发生部分，用于当fs是数据传送频率时产生具有基本上1 /（4×ffs）的脉冲宽度的相位比较定时信号，并且与输出同步地产生具有大致1（2xfs）的脉冲宽度的接收数据再生信号 的边缘检测装置; 与相位比较定时信号相位同步的相位同步振荡部，用于输出频率为数据传送频率fs的n倍的信号; 以及采样部，包括用于通过将从相位同步振荡装置输出的信号的频率除以1 / n来产生位同步信号的装置，用于基于位同步信号对接收数据再生信号进行采样的装置， 信号转换为串行二进制数据。

公开(公告)号：US5905406A

公开(公告)日：1999-05-18

申请号：US845965

申请日：1997-04-30

Applicant: David Mark Sugden ,  Andrew Martin Roberts

Inventor： David Mark Sugden ,  Andrew Martin Roberts

IPC: H04L25/48 ,  H04L25/49 ,  H03D3/00 ,  H03K9/08

CPC classification number: H04L25/4902

Abstract: A demodulator for a pulse width modulated signal comprises a counter arranged to count in one direction when the PWM signal is "high" and in the opposite direction when the PWM signal is "low" to arrive at a count representative of a duty cycle. As a result, a value representative of the duty ratio of the PWM signal can be obtained from the up/down counter. In a further embodiment, the up/down counter is clocked by the output of a frequency multiplier, the output of the frequency multiplier having a frequency determined by the pulse width modulated signal frequency multiplied by a predetermined factor. The value of the duty ratio of the PWM signal can then be found regardless of the frequency of the PWM signal.

Abstract translation: 用于脉冲宽度调制信号的解调器包括计数器，当PWM信号为“高”时，被布置为在一个方向上计数，并且当PWM信号为“低”时反方向，以得到代表占空比的计数。 结果，可以从上/下计数器获得表示PWM信号占空比的值。 在另一实施例中，上/下计数器由倍频器的输出计时，倍频器的输出具有由脉宽调制信号频率乘以预定因子确定的频率。 然后可以发现PWM信号的占空比的值，而不管PWM信号的频率如何。

公开(公告)号：US5680417A

公开(公告)日：1997-10-21

申请号：US320364

申请日：1994-10-11

Applicant: Dennis H. Carlson

Inventor： Dennis H. Carlson

IPC: H04L25/48 ,  H04L27/20 ,  H04B3/00 ,  H04L25/00

CPC classification number: H04L27/2035

Abstract: A binary phase shift keyed (BPSK) modulator (200) used for digital phase modulation is shown. Phase shift is achieved by electrically switching an RF input signal (201) through either a direct signal path (203) or through a half wave transmission signal path (205) to shift its phase by 180 degrees. Both the data signal (211) and its complement (213) are used to turn on one of PIN diodes (207, 209) while simultaneously turning off the other diode with reverse bias. This technique allows for obtaining maximum diode isolation. The BPSK modulator (200) has the advantages of very low insertion loss, dc coupling for low frequency modulation components and high performance with minimum parts.

Abstract translation: 示出了用于数字相位调制的二进制相移键控（BPSK）调制器（200）。 通过直接信号路径（203）或半波传输信号路径（205）将RF输入信号（201）电切换以将其相位移位180度来实现相移。 数据信号（211）和其补码（213）都用于打开PIN二极管（207,209）中的一个，同时以反向偏压同时关闭另一个二极管。 这种技术允许获得最大的二极管隔离。 BPSK调制器（200）具有非常低的插入损耗，低频调制部件的直流耦合和最小部件的高性能优点。

公开(公告)号：US5627885A

公开(公告)日：1997-05-06

申请号：US195628

申请日：1994-02-14

Applicant: Eric Paneth ,  Mordechai Segal ,  Boaz Rippin ,  Ehud H. Rokach

Inventor： Eric Paneth ,  Mordechai Segal ,  Boaz Rippin ,  Ehud H. Rokach

IPC: H03H21/00 ,  H04B3/23 ,  H04L7/04 ,  H04L7/06 ,  H04L7/10 ,  H04L25/00 ,  H04L25/03 ,  H04L25/48 ,  H04M11/00

CPC classification number: H04L25/00 ,  H04B3/23 ,  H04L25/03057 ,  H04L25/03866 ,  H04L7/043 ,  H04L7/06 ,  H04L7/10

Abstract: Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.3) transmitted at the other end of the telephone line. The detector either extracts the digital information based on peaks in the received (non-equalized) signal or by adding the equalized signals with preset threshold values. A scrambler-descrambler module locally generates a replica of the digital symbols transmitted in analog form at the other end of the telephone line, based on a limited number (e.g. 23) of correctly detected digital values. The scrambler-descrambler module may also operate as a descrambler to recover data scrambled by the transmitter at the other end.

Abstract translation: 表示各个数字值（+/- 1，+/- 3）的模拟信号通过电话线路传送到接收器。 这些信号可以首先以伪随机序列提供。 线性回波消除器和第一加法器在一定程度上消除由接收器在相同电话线上发送的第二模拟信号产生的回波信号。 非线性回波消除器和第二加法器进一步减少回波信号并且具体地减少回波信号中的非线性分量。 可调节的信号延迟实现了线性和非线性回波消除器的最佳性能。 包含四（4）个不同模块的均衡器然后补偿由电话线引入的信号失真，并最大限度地减少电话线路中噪声的影响。 均衡器模块是数字增益控制元件，前馈数字滤波器和两（2）个反馈数字滤波器。 检测器模块在接收机处以几种不同的方式之一产生在电话线的另一端传输的数字数据（+/- 1，+/- 3）的估计。 检测器根据接收（非均衡）信号中的峰值提取数字信息，或通过将均衡信号与预设阈值相加。 扰码解扰器模块基于有限数量（例如23个）正确检测的数字值本地生成在电话线的另一端以模拟形式传输的数字符号的副本。 加扰器解扰器模块还可以作为解扰器来操作，以恢复另一端由发射机加扰的数据。

公开(公告)号：US5621758A

公开(公告)日：1997-04-15

申请号：US591718

申请日：1996-01-25

Applicant: Shinichi Suzuki ,  Hirofumi Yamazoe

Inventor： Shinichi Suzuki ,  Hirofumi Yamazoe

IPC: H03M5/08 ,  H04L1/24 ,  H04L25/48 ,  H04L25/49 ,  H03K9/08

CPC classification number: H04L1/246 ,  H03M5/08 ,  H04L25/4902

Abstract: A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.

Abstract translation: 数据输出部分以预定的周期发送具有根据发送数据的值的脉冲宽度的脉冲信号。 H脉冲宽度计数器和L脉冲宽度计数器通过使用具有与在所述时钟信号中使用的时钟信号相同的频率的时钟信号来测量所接收的脉冲信号中的高电平周期的长度和低电平周期的长度 数据输出部分。 比较部分将测量的周期长度与预定周期进行比较，并且在不匹配的情况下输出误差信号。 在PWM通信系统中，也可以检测在一个周期内暂时引起的时钟信号的信号延迟或误差。

公开(公告)号：US5365350A

公开(公告)日：1994-11-15

申请号：US146736

申请日：1993-11-04

Applicant: Masahiro Kawasaki ,  Teruhiko Naruo ,  Yutaka Ohsawa ,  Isamu Hashimoto

Inventor： Masahiro Kawasaki ,  Teruhiko Naruo ,  Yutaka Ohsawa ,  Isamu Hashimoto

IPC: G08C19/28 ,  H04L25/48 ,  H04N1/41

CPC classification number: G08C19/28

Abstract: A method for performing data communication between two circuits. Information is serially transmitted between two circuits. A first level change in one direction of a pulse signal output from one of the circuits to the other is determined as a reference time. A first data bit is determined to be a "1" or "0" in accordance with a time period from the reference time to a second level change in the one direction following the reference time. The second level change in the one direction as the reference time relative to the next bit of data in the pulse signal is then determined, whereby data of a predetermined number of bits are continuously transmitted.

Abstract translation: 一种用于在两个电路之间执行数据通信的方法。 信息在两个电路之间串行传输。 将从一个电路输出的脉冲信号的一个方向上的第一电平变化确定为参考时间。 根据从参考时间之后的一个方向的从基准时间到第二电平变化的时间段，将第一数据位确定为“1”或“0”。 然后，确定相对于脉冲信号中的下一位数据的参考时间的一个方向上的第二电平变化，由此连续发送预定数量的位的数据。

公开(公告)号：US5291524A

公开(公告)日：1994-03-01

申请号：US974531

申请日：1992-11-12

Applicant: Eisaburo Itakura ,  Yuichi Kojima

Inventor： Eisaburo Itakura ,  Yuichi Kojima

IPC: H04N7/015 ,  H03M13/23 ,  H03M13/41 ,  H04L25/48 ,  H04N19/00 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44 ,  H04N19/65 ,  H04N19/89 ,  H04L27/06

CPC classification number: H03M13/41

Abstract: A Viterbi decoding apparatus for decoding received data by Viterbi decoding comprising a state metric memory circuit, a path memory circuit, and a path decode word decision circuit. The state metric memory circuit stores state metric information obtained by ACS (Adder, Comparator, Selector) processing. The path memory circuit stores path selection information provided by the ACS processing. The path decode word decision circuit weights a plurality of bits with a path decode word of each state according to its degree of likelihood based on state metric information supplied from the state metric memory circuit, cumulatively adding each path decode word obtained by the weighting operation, and comparing a cumulative value obtained by the cumulative adding operation with a preset threshold value to determine decode words. This setup provides sufficiently reliable decode words by a small amount of hardware and in a short processing time to decode, within an average information rate, convolutional codes having information amounting to 30 Mbps or more used in high-definition TV etc.

Abstract translation: 一种维特比解码装置，用于通过维特比解码对接收到的数据进行解码，包括状态量度存储电路，路径存储器电路和路径解码字判定电路。 状态度量存储器电路存储由ACS（加法器，比较器，选择器）处理获得的状态度量信息。 路径存储电路存储由ACS处理提供的路径选择信息。 路径解码字决定电路根据从状态量度存储电路提供的状态度量信息，根据其似然程度，对每个状态的路径解码字加权多个位，累积加上通过加权操作获得的每个路径解码字， 以及将通过累积加法运算获得的累积值与预设阈值进行比较，以确定解码字。 该设置通过少量硬件提供足够可靠的解码字，并且在短的处理时间内，在平均信息速率内解码具有高清电视等中使用的30Mbps或更多信息的卷积码。