Abstract:
The problem of being unable to run microBFD using an IPv6 address over any member links of a layer 2 LAG when the LAG is DOWN (and its IPv6 address becomes or is TENTATIVE), is solved by running DAD for the address configured for the microBFD once the individual link is in DISTRIBUTING or STANDBY state and triggering (or starting) microBFD once the DAD for that address completes successfully. Further, member links of the LAG may be permitted to continue running microBFD even if the LAG interface is DOWN and even if some other member links (but not all member links) of the LAG are DOWN.
Abstract:
The present invention relates to a method for conditioning a received signal that transmits coded data, wherein the coding of the data includes a defined coding clock pulse and the signal includes edges produced in accordance with the coding clock pulse, wherein from the received signal a time constant (tm) set in accordance with the coding clock pulse is determined, a first signal part which has a first edge is conditioned at a first time that is set in accordance with the time constant (tm) or in a first time window that is set in accordance with the time constant (tm), and a second signal part which has a second edge is conditioned at a second time that is set in accordance with the time constant (tm) and in dependence on the time of the first edge or in a second time window that is set in accordance with the time constant (tm) and in dependence on the time of the first edge.
Abstract:
A delay-locked loop which phase-locks the reference clock of crystal oscillation by certain identical delay units for generating certain precise time-sharing phase signals. These time-sharing phase signals can be utilized to recover the clock/data. The advantages of the invention, when comparing with the typical phase-locked loop, are: (1) it can be easily stabilized; (2) the phase error does not accumulate; (3) the loop filter requires only one capacitor, which reduces the area of chip; (4) no additional loop filter is need in multiport application, which further reduces the area of chip.
Abstract:
A data decoding circuit of the present invention can regenerate a bit synchronization signal from a data received by using a code such as a split-phase code and Manchester code in which a binary value can be detected through a transition of voltage at a central area of a bit cell and transform the received data into a serial binary data. The data decoding circuit includes an edge detection section for detecting a transition point in the received data; a pulse generating section for generating a phase comparing timing signal having a pulse width of substantially 1/(4.times.fs) when fs is a data transfer frequency and a received data regenerating signal having a pulse width of substantially 1(2.times.fs) in synchronism with an output of the edge detection means; a phase synchronization oscillation section synchronized in phase with the phase comparing timing signal for outputting a signal having a frequency n times the data transfer frequency fs; and a sampling section including means for generating the bit synchronization signal by dividing a frequency of a signal outputted from the phase synchronization oscillation means into 1/n, means for sampling the received data regenerating signal based on the bit synchronization signal and means for transforming sampled signal into a serial binary data.
Abstract:
A demodulator for a pulse width modulated signal comprises a counter arranged to count in one direction when the PWM signal is "high" and in the opposite direction when the PWM signal is "low" to arrive at a count representative of a duty cycle. As a result, a value representative of the duty ratio of the PWM signal can be obtained from the up/down counter. In a further embodiment, the up/down counter is clocked by the output of a frequency multiplier, the output of the frequency multiplier having a frequency determined by the pulse width modulated signal frequency multiplied by a predetermined factor. The value of the duty ratio of the PWM signal can then be found regardless of the frequency of the PWM signal.
Abstract:
A binary phase shift keyed (BPSK) modulator (200) used for digital phase modulation is shown. Phase shift is achieved by electrically switching an RF input signal (201) through either a direct signal path (203) or through a half wave transmission signal path (205) to shift its phase by 180 degrees. Both the data signal (211) and its complement (213) are used to turn on one of PIN diodes (207, 209) while simultaneously turning off the other diode with reverse bias. This technique allows for obtaining maximum diode isolation. The BPSK modulator (200) has the advantages of very low insertion loss, dc coupling for low frequency modulation components and high performance with minimum parts.
Abstract:
Analog signals representing individual digital values (.+-.1, .+-.3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo signals resulting from second analog signals transmitted on the same telephone line by the receiver. A non-linear echo canceller and a second adder further reduce the echo signals and specifically reduce non-linear components in the echo signals. Adjustable signal delays achieve optimal performance of the linear and non-linear echo cancellers. An equalizer containing four (4) different modules then compensates for signal distortions introduced by the telephone line and minimizes the effect of noise in the telephone line. The equalizer modules are a digital gain control element, a feed forward digital filter and two (2) feedback digital filters. A detector module produces in one of several different ways at the receiver an estimate of the digital data (.+-.1, .+-.3) transmitted at the other end of the telephone line. The detector either extracts the digital information based on peaks in the received (non-equalized) signal or by adding the equalized signals with preset threshold values. A scrambler-descrambler module locally generates a replica of the digital symbols transmitted in analog form at the other end of the telephone line, based on a limited number (e.g. 23) of correctly detected digital values. The scrambler-descrambler module may also operate as a descrambler to recover data scrambled by the transmitter at the other end.
Abstract:
A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.
Abstract:
A method for performing data communication between two circuits. Information is serially transmitted between two circuits. A first level change in one direction of a pulse signal output from one of the circuits to the other is determined as a reference time. A first data bit is determined to be a "1" or "0" in accordance with a time period from the reference time to a second level change in the one direction following the reference time. The second level change in the one direction as the reference time relative to the next bit of data in the pulse signal is then determined, whereby data of a predetermined number of bits are continuously transmitted.
Abstract:
A Viterbi decoding apparatus for decoding received data by Viterbi decoding comprising a state metric memory circuit, a path memory circuit, and a path decode word decision circuit. The state metric memory circuit stores state metric information obtained by ACS (Adder, Comparator, Selector) processing. The path memory circuit stores path selection information provided by the ACS processing. The path decode word decision circuit weights a plurality of bits with a path decode word of each state according to its degree of likelihood based on state metric information supplied from the state metric memory circuit, cumulatively adding each path decode word obtained by the weighting operation, and comparing a cumulative value obtained by the cumulative adding operation with a preset threshold value to determine decode words. This setup provides sufficiently reliable decode words by a small amount of hardware and in a short processing time to decode, within an average information rate, convolutional codes having information amounting to 30 Mbps or more used in high-definition TV etc.