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公开(公告)号：US11640255B2
公开(公告)日：2023-05-02
申请号：US17518624
申请日：2021-11-04
发明人： Wei-Chen Wang , Ting-Hsuan Lo , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
摘要： Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.
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公开(公告)号：US11594277B2
公开(公告)日：2023-02-28
申请号：US17871811
申请日：2022-07-22
发明人： Shu-Yin Ho , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G06N3/06 , G06N3/08 , G06F7/544 , G11C11/4091 , G11C11/408 , G11C11/4094
摘要： A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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公开(公告)号：US20220359003A1
公开(公告)日：2022-11-10
申请号：US17871811
申请日：2022-07-22
发明人： Shu-Yin Ho , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G11C11/4091 , G11C11/408 , G06N3/06 , G06N3/08 , G06F7/544 , G11C11/4094
摘要： A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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公开(公告)号：US11443797B2
公开(公告)日：2022-09-13
申请号：US16798166
申请日：2020-02-21
发明人： Shu-Yin Ho , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G11C11/4091 , G06N3/06 , G06N3/08 , G06F7/544 , G11C11/408 , G11C11/4094
摘要： A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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公开(公告)号：US20200312405A1
公开(公告)日：2020-10-01
申请号：US16798166
申请日：2020-02-21
发明人： SHU-YIN HO , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G11C11/4091 , G11C11/408 , G11C11/4094 , G06N3/06 , G06N3/08 , G06F7/544
摘要： A method and an apparatus for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, are provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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