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    MEMORY DEVICE AND OPERATION METHOD THEREOF
    2.
    发明公开
    MEMORY DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20230161556A1

    公开(公告)日：2023-05-25

    申请号：US17701725

    申请日：2022-03-23

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： Han-Wen Hu ,  Yung-Chun Li ,  Bo-Rong Lin ,  Huai-Mu Wang ,  Wei-Chen Wang

    IPC分类号： G06F7/544 ,  G06F7/527 ,  G06F7/72 ,  G06F12/0882 ,  G06F13/16

    CPC分类号： G06F7/5443 ,  G06F7/5272 ,  G06F7/729 ,  G06F12/0882 ,  G06F13/1673

    摘要： A memory device and an operation method thereof are provided. The operation method includes: encoding an input data, sending an encoded input data to at least one page buffer, and reading out the encoded input data in parallel; encoding a first part and a second part of a weight data into an encoded first part and an encoded second part of the weight data, respectively, writing the encoded first part and the encoded second part of the weight data into a plurality of memory cells of the memory device, and reading out the encoded first part and the encoded second part of the weight data in parallel; multiplying the encoded input data with the encoded first part and the encoded second part of the weight data respectively to parallel generate a plurality of partial products; and accumulating the partial products to generate an operation result.

    Apparatus and method for efficient modular exponentiation
    4.
    发明授权
    Apparatus and method for efficient modular exponentiation 失效
    用于有效模幂的装置和方法

    公开(公告)号：US06917956B2

    公开(公告)日：2005-07-12

    申请号：US09929462

    申请日：2001-08-14

    申请人： Leonard D. Rarick

    发明人： Leonard D. Rarick

    IPC分类号： G06F7/52 ,  G06F7/527 ,  G06F7/72

    CPC分类号： G06F7/728 ,  G06F7/5275

    摘要： An improved apparatus and method for modular multiplication and exponentiation to achieve efficient computation involved in Montgomery multiplication is provided. Currently employed conventional iteration methods involve carry look-ahead additions. To overcome the time taken by carry look-ahead additions, there is thus provided, in accordance with a preferred embodiment of the present invention, an apparatus and method for separately storing and tracking the sum and the carry of the addition involved in Montgomery multiplication. In such a manner, the present invention achieves fast addition times since they are not dependent on the time to compute the carries. As a result, the iterations are carried out much faster than previously possible. By representing the value A in the Montgomery multiplication algorithm with a redundant notation, the sum and the carry of the addition are separately stored and tracked, thereby avoiding the delays involved in the computation of the carries. In such a manner, by separately storing and tracking the sum and the carry of the addition, this carry-save addition enables a much faster computation involved in Montgomery multiplication.

    摘要翻译： 提供了一种改进的用于模数乘法和乘幂的装置和方法，以实现蒙哥马利乘法中涉及的有效计算。 目前使用的常规迭代方法涉及携带预先添加。 为了克服携带预先添加所花费的时间，根据本发明的优选实施例，提供了一种用于分别存储和跟踪蒙哥马利乘法中所涉及的加法和进位的装置和方法。 以这种方式，本发明实现了快速的加法时间，因为它们不依赖于计算载体的时间。 因此，迭代执行得比以前更快。 通过用冗余符号表示蒙哥马利乘法算法中的值A，分别存储和跟踪加法的和和进位，从而避免了运算计算中涉及的延迟。 以这种方式，通过分别存储和跟踪加法和加法的进位，该进位保存附加使得在蒙哥马利乘法中涉及的计算速度更快。

    1-bit adder and multiplier containing a 1-bit adder
    6.
    发明授权
    1-bit adder and multiplier containing a 1-bit adder 失效
    1位加法器和包含1位加法器的乘法器

    公开(公告)号：US5515309A

    公开(公告)日：1996-05-07

    申请号：US211898

    申请日：1994-06-20

    申请人： Joseph C. Y. Fong

    发明人： Joseph C. Y. Fong

    IPC分类号： G06F7/507 ,  G06F7/50 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53 ,  G06F7/533 ,  H03K19/0944

    CPC分类号： G06F7/5338 ,  G06F7/501 ,  G06F7/507 ,  H03K19/09448 ,  G06F2207/3884 ,  G06F2207/4812 ,  G06F2207/4816

    摘要： A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which consist of a PMOS and an NMOS transistor. The source of the PMOS transistor is connected with the drain of the NMOS transistor and the drain of the PMOS transistor is connected with the source of the NMOS transistor. The gate of the PMOS transistor receives inverted signals with respect to the gate of the NMOS transistor. Two partial output sum signals are generated by two of the switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of the adder is available at the output of the inverter.A fast multiplier includes (i) a plurality of the above fast one-bit adders, (ii) reduction of partial products by application of a Booth-McSorley process, (iii) diagonal propagation of caries from one partial product to another allowing all sums on one line to be done simultaneously, and (iv) application of a carry select approach in the final 14 bits and in the first two adders in intermediate rows.

    摘要翻译： PCT No.PCT / EP92 / 02350 Sec。 371日期：1994年6月20日 102（e）日期1994年6月20日PCT提交1992年10月12日PCT公布。 出版物WO93 / 08523 日期为1993年04月29日。一位加法器包括进位级和加法级，并且在由PMOS和NMOS晶体管组成的加法级中的互补模拟CMOS开关的快速CMOS互补通道晶体管逻辑中构成。 PMOS晶体管的源极与NMOS晶体管的漏极连接，PMOS晶体管的漏极与NMOS晶体管的源极连接。 PMOS晶体管的栅极相对于NMOS晶体管的栅极接收反相信号。 两个部分输出和信号分别由与反相器的输入端和输出端连接的两个开关产生，加法器的输出和信号在反相器的输出端可用。 快速乘法器包括（i）多个上述快速一位加法器，（ii）通过应用Booth-McSorley过程减少部分乘积，（iii）龋齿从一个部分乘积到另一部分乘积的对角线传播，允许所有的和 在一行要同时完成，以及（iv）在最后14位和中间行的前两个加法器中应用进位选择方法。

    Cellular multiplier comprising a tree of the overturned stairs type, and method of implementation
    7.
    发明授权
    Cellular multiplier comprising a tree of the overturned stairs type, and method of implementation 失效
    包括翻转楼梯类型的树的蜂窝乘法器和实现方法

    公开(公告)号：US5497342A

    公开(公告)日：1996-03-05

    申请号：US338159

    申请日：1994-11-09

    申请人： Zhi-Jian Mou ,  Francis Jutand

    发明人： Zhi-Jian Mou ,  Francis Jutand

    IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/527 ,  G06F7/50

    CPC分类号： G06F7/5318

    摘要： A multiplier of order p and of depth n+1 is formed by a root R constituted by a carry-save adder and by a multiplier body CO(p,n) of order p and of depth n formed by a five-input connector operator C(n,q) of rank q, the connector operator C(n,1) of rank 1 is connected to the root R, the connector operator C(n,q) of rank q comprising first and second carry-save adders (1, 2) connected in cascade. The multiplier body CO(p,n) further includes a tree A(p-1,n-2) of order p-1 and of depth n-2 formed by an arrangement of carry-save adders and connected to the first carry-save adder (1), and a multiplier body CO(p,n-1 ) of order p and of lesser depth n-1 formed analogously to the multiplier body CO(p,n) of greater depth n by recurrence, the multiplier body CO(p,n-1) of lesser depth being connected to the connector operator C(n,q). The multiplier is applicable to performing calculations and to implementing digital filters.

    摘要翻译： 阶数_p和深度n + 1的乘数由由进位保存加法器和乘数体CO（p，n）构成的根R形成，并且由乘法器主体CO（p，n）和由五输入连接器运算符形成的深度_n 等级为q的C（n，q），等级1的连接器操作器C（n，1）连接到根R，包括第一和第二进位保存加法器的等级_q的连接器运算符C（n，q） 1，2）级联连接。 乘法器体CO（p，n）还包括由进位保存加法器的布置形成的p-1阶的树A（p-1，n-2）和深度n-2，并连接到第一进位 - 乘法器本体CO（p，n-1）的乘积体CO（p，n-1）和较小深度n-1的乘法器体CO（p，n-1）类似于通过复现而具有较大深度n的乘法器体CO（p，n） 较小深度的CO（p，n-1）连接到连接器操作器C（n，q）。 乘数适用于执行计算和实现数字滤波器。

    Method for generating hardware description of multiplier and/or multiplier-adder
    8.
    发明授权
    Method for generating hardware description of multiplier and/or multiplier-adder 失效
    用于产生乘法器和/或乘法器加法器的硬件描述的方法

    公开(公告)号：US5473558A

    公开(公告)日：1995-12-05

    申请号：US184628

    申请日：1994-01-21

    申请人： Kenichiro Nakamura

    发明人： Kenichiro Nakamura

    IPC分类号： G06F7/52 ,  G06F7/523 ,  G06F7/527 ,  G06F7/544 ,  G06F17/10 ,  G06F17/50 ,  G06F7/00 ,  G06F15/00

    CPC分类号： G06F7/53 ,  G06F17/5045 ,  G06F7/5443

    摘要： A method for generating a hardware description of a multiplier/multiplier-adder for integrating a signal processing circuit includes the steps of acquiring input parameters such as a word length of multiplier factor, generating a first hardware description of a first add for adding partial products and an inputs addend, determining a redundancy index r by using the input parameters, generating a second hardware description of a second add circuit for performing a carry-add of every r bits of the output of the first add circuit, and replacing useless circuits from the hardware descriptions.

    摘要翻译： 一种用于生成用于对信号处理电路进行积分的乘法器/乘法器加法器的硬件描述的方法包括以下步骤：获取诸如乘法器系数的字长的输入参数，生成用于添加部分乘积的第一加法的第一硬件描述， 输入加法，通过使用输入参数确定冗余索引r，产生第二加法电路的第二硬件描述，用于执行第一加法电路的输出的每个r位的进位加法，以及从第 硬件说明。

    Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression
    9.
    发明授权
    Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression 失效
    用于自定时单调逻辑进程的矢量逻辑方法和动态捕鼠器逻辑门

    公开(公告)号：US5389835A

    公开(公告)日：1995-02-14

    申请号：US14881

    申请日：1993-02-03

    申请人： Jeffry D. Yetter

    发明人： Jeffry D. Yetter

    IPC分类号： G06F7/38 ,  G06F7/50 ,  G06F7/52 ,  G06F7/527 ,  G06F7/53 ,  G06F7/533 ,  H03K19/00 ,  H03K19/094 ,  H03K19/096 ,  H03K19/21

    CPC分类号： G06F7/5338 ,  G06F7/501 ,  G06F7/5016 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0966 ,  H03K19/215 ,  G06F2207/3872

    摘要： A dynamic mousetrap logic gate implements a self-timed monotonic logic progression via a novel vector logic method. In the vector logic method, a vector logic variable is defined by a plurality of vector components situated on respective logic paths. Boolean as well as non-Boolean variables can be represented. Further, timing information is encoded in the vector logic variable itself by defining the vector logic variable as invalid when all the vector components currently exhibit a logic low and by defining the vector logic variable as valid when a subset of the vector components exhibits a logic high. With a plurality of valid vector logic states, subsets defining valid vector logic states are nonoverlapping. The mousetrap logic gate comprises a plurality of gate components in parallel, corresponding with each output vector component. Each gate component has an arming mechanism, a ladder logic, and an inverting buffer mechanism. The ladder logic performs logic functions on one or more input vectors and provides the result to the inverting buffer mechanism. The arming mechanism periodically precharges the inverting buffer input to drive the gate component output to a logic low until the inverting buffer mechanism is triggered by the ladder logic.

    摘要翻译： 动态捕鼠器逻辑门通过新颖的矢量逻辑方法实现自定时单调逻辑进程。 在矢量逻辑方法中，矢量逻辑变量由位于相应逻辑路径上的多个矢量分量定义。 可以表示布尔值以及非布尔变量。 此外，当向量逻辑变量本身通过将所有向量分量当前呈现逻辑低的矢量逻辑变量定义为无效时，通过将矢量逻辑变量定义为有效，当矢量分量的子集呈现逻辑高时，定时信息被编码在矢量逻辑变量本身中 。 利用多个有效向量逻辑状态，限定有效向量逻辑状态的子集是不重叠的。 捕鼠器逻辑门包括与每个输出向量分量对应的并行的多个门组件。 每个门组件具有布防机制，梯形逻辑和反相缓冲机构。 梯形逻辑在一个或多个输入向量上执行逻辑功能，并将结果提供给反相缓冲机制。 布防机制周期性地对反相缓冲器输入进行预充电，以将栅极分量输出驱动到逻辑低电平，直到反相缓冲器机构被梯形逻辑触发。