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公开(公告)号：US10019229B2
公开(公告)日：2018-07-10
申请号：US14748924
申请日：2015-06-24
发明人： Thomas Elmer
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor comprises an instruction execution unit operable to generate an intermediate result vector and a plurality of calculation control indicators and storage external to the instruction execution unit which stores the intermediate result vector and the plurality of calculation control indicators. The intermediate result vector is generated from an application of at least a first arithmetic operation of a compound arithmetic operation. The calculation control indicators indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The subsequent calculations may involve one or more remaining arithmetic operations of the compound arithmetic operation. The intermediate result vector, in combination with the plurality of calculation control indicators, provides sufficient information to generate a result indistinguishable from an infinitely precise calculation of the compound arithmetic operation whose result is reduced in significance to a target data size.
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公开(公告)号：US09891887B2
公开(公告)日：2018-02-13
申请号：US14749088
申请日：2015-06-24
发明人： Thomas Elmer
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.
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公开(公告)号：US09891886B2
公开(公告)日：2018-02-13
申请号：US14749050
申请日：2015-06-24
发明人： Thomas Elmer
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C. An evaluation is made to detect whether values of A, B, and/or C meet a sufficient condition for performing a joint accumulation of C with partial products of A and B. If so, a joint accumulation of C is done with partial products of A and B and result of the joint accumulation is rounded. If not, then a primary accumulation is done of the partial products of A and B. This generates an unrounded non-redundant result of the primary accumulation. The unrounded result is then truncated to generate an unrounded non-redundant intermediate result vector that excludes one or more least significant bits of the unrounded non-redundant result. A secondary accumulation is then performed, adding or subtracting C to the unrounded non-redundant intermediate result vector. Finally, the result of the secondary accumulation is rounded.
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公开(公告)号：US09851946B2
公开(公告)日：2017-12-26
申请号：US15470692
申请日：2017-03-27
CPC分类号： G06F7/49957 , G06F7/386 , G06F7/483 , G06F7/491 , G06F7/49915 , G06F7/49947 , G06F7/49963 , G06F7/49968 , G06F7/49973 , G06F7/49978 , G06F7/49984 , G06F9/30014 , G06F17/10
摘要： A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
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公开(公告)号：US09690544B2
公开(公告)日：2017-06-27
申请号：US14943254
申请日：2015-11-17
CPC分类号： G06F7/49957 , G06F7/386 , G06F7/483 , G06F7/491 , G06F7/49915 , G06F7/49947 , G06F7/49963 , G06F7/49968 , G06F7/49973 , G06F7/49978 , G06F7/49984 , G06F9/30014 , G06F17/10
摘要： A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
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6.发明申请公开(公告)号：US20170083479A1
公开(公告)日：2017-03-23
申请号：US15272994
申请日：2016-09-22
发明人： Seong Woo AHN , Hyung Jong KIM , Hyun Woo SIM , Hun Kee KIM
IPC分类号： G06F17/14
CPC分类号： H04L27/00 , G06F7/00 , G06F7/49957 , H04L27/0002
摘要： A digital signal processor is provided. The digital signal processor includes an execution circuit configured to receive a first data including first bits expressed in a signed magnitude method and a second data including second bits expressed in the signed magnitude method, and a control logic circuit configured to output a control signal that determines a type of operation on the first data and the second data based on a command signal, wherein the execution circuit is further configured to perform an operation on the first data and the second data according to a determined type of operation and generate a result of the operation.
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公开(公告)号：US09489174B2
公开(公告)日：2016-11-08
申请号：US14498183
申请日：2014-09-26
发明人： Leonard Rarick
CPC分类号： G06F7/483 , G06F7/49957 , G06F7/5443
摘要： Embodiments disclosed pertain to apparatuses, systems, and methods for floating point operations. Disclosed embodiments pertain to a circuit that is capable of processing both a normal and denormal inputs and outputting normal and denormal results, and where a rounding module is used advantageously to reduce operational latency of the circuit.
摘要翻译： 所公开的实施例涉及用于浮点运算的装置，系统和方法。 公开的实施例涉及能够处理正常和非正常输入并输出正常和非正常结果的电路，并且其中有利地减少舍入模块以减少电路的操作等待时间。
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8.发明授权公开(公告)号：US09483232B2
公开(公告)日：2016-11-01
申请号：US14200923
申请日：2014-03-07
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess
CPC分类号： G06F7/4876 , G06F5/012 , G06F7/49952 , G06F7/49957 , G06F7/5336 , G06F2207/483
摘要： A data processing apparatus and method are provided for multiplying first and second normalized floating point operands in order to generate a result, each normalized floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalized version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalized floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalized result significand. Thereafter, the normalized result significand is shifted in a second direction opposite to the first direction, by the shift amount, in order to generate a rounded result significand. This provides a particularly efficient mechanism for multiplying floating point numbers, while correctly rounding the result in situations where the result is subnormal.
摘要翻译： 提供了一种数据处理装置和方法，用于对第一和第二标准化浮点操作数进行乘法，以便产生结果，每个归一化浮点操作数包括有效位数和指数。 指数确定电路用于计算结果的归一化版本的结果指数，并且舍入值生成电路然后通过将第一方向上的舍入常数移位取决于结果指数的移位量来生成舍入值。 部分产品生成电路将第一和第二标准化浮点运算数的有效数乘以生成第一和第二部分乘积，然后将第一和第二部分乘积与舍入值一起加在一起，以便生成归一化结果 有意义 此后，归一化结果有效位置在与第一方向相反的第二方向上移位移位量，以产生舍入结果有效。 这提供了一种用于乘以浮点数的特别有效的机制，同时在结果为非正常的情况下正确地舍入结果。
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公开(公告)号：US20160004508A1
公开(公告)日：2016-01-07
申请号：US14749088
申请日：2015-06-24
发明人： THOMAS ELMER
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.
摘要翻译： 微处理器通过向一个或多个指令执行单元发出第一和第二乘法累加微指令来完成融合乘法累加操作，准备形式为±A * B±C的融合乘法累加运算。 第一个乘法累加微指令通过（a）A和B的部分乘积或（b）C与A和B的部分乘积的所选择的一个的第一次累积产生未被包围的非冗余结果向量。第二个 如果第一次累积不包括C，则乘法累加微指令会导致C的第二次累积与未被包围的非冗余结果向量的性能。第二乘法累加微指令还导致从未被包围的非冗余结果向量生成最终舍入结果， 其中最终舍入结果是融合乘法累加操作的完整结果。
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公开(公告)号：US20160004507A1
公开(公告)日：2016-01-07
申请号：US14749050
申请日：2015-06-24
发明人： THOMAS ELMER
CPC分类号： G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/3001 , G06F9/30014 , G06F9/3017 , G06F9/30185 , G06F9/38 , G06F9/3893 , G06F17/16
摘要： A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C. An evaluation is made to detect whether values of A, B, and/or C meet a sufficient condition for performing a joint accumulation of C with partial products of A and B. If so, a joint accumulation of C is done with partial products of A and B and result of the joint accumulation is rounded. If not, then a primary accumulation is done of the partial products of A and B. This generates an unrounded non-redundant result of the primary accumulation. The unrounded result is then truncated to generate an unrounded non-redundant intermediate result vector that excludes one or more least significant bits of the unrounded non-redundant result. A secondary accumulation is then performed, adding or subtracting C to the unrounded non-redundant intermediate result vector. Finally, the result of the secondary accumulation is rounded.
摘要翻译： 微处理器执行形式为±A * B±C的融合乘法累加运算。 进行评价以检测A，B和/或C的值是否满足用于对A和B的部分乘积进行C的联合积累的充分条件。如果是，则C的共同积累是 A和B以及联合积累的结果是四舍五入的。 如果不是，则对A和B的部分乘积进行一次累积。这产生一次积累的未被包围的非冗余结果。 然后将未包围的结果截断，以生成一个未包围的非冗余中间结果向量，排除非周期非冗余结果的一个或多个最低有效位。 然后执行二次累加，向未包围的非冗余中间结果向量添加或减去C。 最后，二次积累的结果是四舍五入的。
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