公开(公告)号：US09305638B1

公开(公告)日：2016-04-05

申请号：US14526560

申请日：2014-10-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Chih-Chang Hsieh ,  Shih-Fu Huang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.

Abstract translation: 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。

公开(公告)号：US20160064103A1

公开(公告)日：2016-03-03

申请号：US14474382

申请日：2014-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ying-Tsai Ting ,  Che-Chin Wu ,  Tsung-Yi Chou ,  Shih-Fu Huang

IPC: G11C29/38

CPC classification number: G11C29/38 ,  G11C17/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/702 ,  G11C2029/1204

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract translation: 测试方法测试包括具有多个对称存储器单元，多个字线和多个位线的存储器阵列的存储器件。 在测试第一字线时，对第一位线进行充电以测试相邻第一对称存储器单元的前半部分的单个位; 并且第二位线被充电以测试相邻第二对称存储器单元的第二半的单个位。 在测试第二字线时，对第一位线进行充电以测试相邻第三对称存储器单元的第二半的单个位; 并且第二位线被充电以测试相邻第四对称存储器单元的前半部分的单个位。 在测试每个字线时，每个位线都被充电一次。

公开(公告)号：US09548138B2

公开(公告)日：2017-01-17

申请号：US14474382

申请日：2014-09-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ying-Tsai Ting ,  Che-Chin Wu ,  Tsung-Yi Chou ,  Shih-Fu Huang

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/42 ,  G11C29/44 ,  G11C17/00 ,  G11C29/12

CPC classification number: G11C29/38 ,  G11C17/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/702 ,  G11C2029/1204

Abstract: A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.

Abstract translation: 测试方法测试包括具有多个对称存储器单元，多个字线和多个位线的存储器阵列的存储器件。 在测试第一字线时，对第一位线进行充电以测试相邻第一对称存储器单元的前半部分的单个位; 并且第二位线被充电以测试相邻第二对称存储器单元的第二半的单个位。 在测试第二字线时，对第一位线进行充电以测试相邻第三对称存储器单元的第二半的单个位; 并且第二位线被充电以测试相邻第四对称存储器单元的前半部分的单个位。 在测试每个字线时，每个位线都被充电一次。