公开(公告)号：US09817588B2

公开(公告)日：2017-11-14

申请号：US14683630

申请日：2015-04-10

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Ming Chang ,  Wei-Chieh Huang ,  Li-Chun Huang ,  Hung-Sheng Chang ,  Hsiang-Pang Li ,  Ting-Yu Liu ,  Chien-Hsin Liu ,  Nai-Ping Kuo

IPC: G06F3/06 ,  G06F12/0806

CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0806 ,  G06F2212/621

Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

公开(公告)号：US09754637B2

公开(公告)日：2017-09-05

申请号：US15212340

申请日：2016-07-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Hsiang-Pang Li ,  Hsin-Yu Chang ,  Chien-Chung Ho ,  Yuan-Hao Chang

IPC: G11C7/00 ,  G11C16/00 ,  G11C16/16 ,  G11C16/14

CPC classification number: G11C7/00 ,  G11C16/14 ,  G11C16/16

Abstract: An erasing method and a memory device are provided. The memory device includes a plurality of memory blocks. Each of the memory blocks has n sub-blocks. The erasing method includes the following steps. A first erase region is selected from a first memory block of the memory blocks, and the first erase region includes at least one sub-block. A sub-block erase operation is performed on the first erase region of the first memory block.

公开(公告)号：US20160147464A1

公开(公告)日：2016-05-26

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F3/06

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

Abstract translation: 一种用于存储器的操作方法，所述存储器包括至少一个存储块，所述至少一个存储块包括与所述第一页对应的多个第一页和多个第二页，所述操作方法包括以下步骤：确定所述第一页的目标第一页 页面是有效的，其中目标第一页面对应于第二页面的目标第二页面; 如果目标第一页有效，则在目标第二页上执行第一类型编程; 如果目标第一页无效，则在目标第二页上执行第二类型编程。

公开(公告)号：US20190087110A1

公开(公告)日：2019-03-21

申请号：US15705309

申请日：2017-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun Li ,  Ping-Hsien Lin ,  Yu-Ming Chang

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0655 ,  G06F3/0688 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3418

Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.

公开(公告)号：US10120605B2

公开(公告)日：2018-11-06

申请号：US15093841

申请日：2016-04-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hung-Sheng Chang ,  Yu-Ming Chang ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

公开(公告)号：US09823961B1

公开(公告)日：2017-11-21

申请号：US15376715

申请日：2016-12-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Huang ,  Yu-Ming Chang ,  Hsi-Chia Chang

IPC: G11C16/06 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G11C7/1006 ,  G11C16/08 ,  G11C16/349 ,  G11C16/3495

Abstract: An operating method of a memory controller, for a memory device including a plurality of cells, includes steps of: checking states of the cells; marking at least one specific bit-channel according to the states of the cells; and performing an uneven wear leveling scheme on at least one target cell storing messages from the at least one specific bit-channel, such that the wear level of the at least one target cell is different from other cells.

公开(公告)号：US09740602B2

公开(公告)日：2017-08-22

申请号：US14805498

申请日：2015-07-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsiang-Pang Li ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F12/00 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7209 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5648

Abstract: An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page.

公开(公告)号：US20140307505A1

公开(公告)日：2014-10-16

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

公开(公告)号：US10445008B2

公开(公告)日：2019-10-15

申请号：US15705309

申请日：2017-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun Li ,  Ping-Hsien Lin ,  Yu-Ming Chang

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F13/00 ,  G06F13/28

Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.

公开(公告)号：US10108555B2

公开(公告)日：2018-10-23

申请号：US15370059

申请日：2016-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yuan-Hao Chang ,  Hsiu-Chang Chen ,  Tei-Wei Kuo

IPC: G06F12/02 ,  G06F12/121 ,  G06F12/00 ,  G06F12/06 ,  G06F12/1009

Abstract: A memory management method includes: providing a hybrid memory comprising a first type memory and a second type memory; providing an inactive list and a read active list for recording in-used pages on the first type memory; providing a write active list for recording in-used pages on the second type memory; allocating a page from the first type memory according to a system request, and inserting the page into the inactive list accordingly; moving the page from the inactive list to the write active list or the read active list in response to two or more successive access operations on the page; and referring the page to a physical address on the second type memory when the page is in the write active list.