公开(公告)号：US09558108B2

公开(公告)日：2017-01-31

申请号：US14018149

申请日：2013-09-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/34 ,  G11C16/04 ,  G11C16/16

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid.

Abstract translation: 提供了一种用于管理块擦除操作的方法，用于包括阵列中的可擦除存储单元块的存储单元阵列。 该方法包括维护阵列的可擦除块的多个子块的状态数据。 状态数据指示子块当前是否可访问以及子块是否无效。 该方法响应于擦除特定可擦除块的所选子块的请求，如果特定可擦除块的其他子块无效则发出擦除命令以擦除特定块，否则更新状态数据 以指示所选择的子块是无效的。

公开(公告)号：US20140307505A1

公开(公告)日：2014-10-16

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。

公开(公告)号：US09411521B2

公开(公告)日：2016-08-09

申请号：US14291998

申请日：2014-05-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsing-Chen Lu ,  Pochao Fang

IPC: G11C8/04 ,  G06F3/06 ,  G11C8/18 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2212/1016 ,  G11C8/04 ,  G11C8/18

Abstract: The present technology is directed to a method for accessing a memory device in response to read requests is described. The method comprises, in response to a first request, composing a first read sequence using a command protocol of the memory device. The first read sequence includes a command code and a starting physical address. Upon receipt of a second request, the method determines a starting physical address of a second read sequence according to the command protocol of the memory device. If the starting physical address of the second read sequence is sequential to an ending physical address of the first read sequence, then the method composes the second read sequence using the command protocol without a command code, else the method composes the second read sequence using the command protocol with a read command.

Abstract translation: 本技术涉及用于响应于读请求访问存储器件的方法。 该方法包括响应于第一请求，使用存储器件的命令协议来组合第一读取序列。 第一读取序列包括命令代码和起始物理地址。 在接收到第二请求时，该方法根据存储器件的命令协议确定第二读取序列的起始物理地址。 如果第二读取序列的起始物理地址与第一个读取序列的结束物理地址相顺序，则该方法使用没有命令代码的命令协议组成第二个读取序列，否则该方法使用 命令协议与读命令。

公开(公告)号：US09025375B2

公开(公告)日：2015-05-05

申请号：US14060296

申请日：2013-10-22

Applicant: Macronix International Co., Ltd.

Inventor： Yu-Ming Chang ,  Yung-Chun Li ,  Hsing-Chen Lu ,  Hsiang-Pang Li ,  Cheng-Yuan Wang ,  Yuan-Hao Chang ,  Tei-Wei Kuo

IPC: G11C16/04 ,  G11C16/34 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3427

Abstract: Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page groups. Access is allowed to memory cells within a first page group of a plurality of page groups in an erase block of the three dimensional NAND array, while access is minimized to memory cells within a second page group of the plurality of page groups in the erase block of the three/two dimensional NAND array. Pages in the same page group are physically nonadjacent with each other in the three/two dimensional NAND array.

Abstract translation: 描述了支持减少非易失性存储器的程序干扰的技术。 三/二维NAND阵列包括被分成多个页组的多页。 允许访问在三维NAND阵列的擦除块中的多个寻呼组的第一页组内的存储单元，同时访问最小化到擦除块中的多个页组的第二页组内的存储单元 的三/二维NAND阵列。 同一页组中的页面在三维/二维NAND阵列中彼此物理上不相邻。