Determining read voltages for memory systems

    公开(公告)号:US11663074B1

    公开(公告)日:2023-05-30

    申请号:US17528346

    申请日:2021-11-17

    Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems are provided. In one aspect, a memory system includes a memory storing data and a memory controller coupled to the memory. The memory controller is configured to: obtain a first reading output of target memory data in the memory using a first read voltage, and in response to determining that the first reading output fails to pass an Error-Correcting Code (ECC) test, provide the first read voltage to the memory. The memory is configured to: determine a second read voltage based on the first read voltage and generate a second reading output of the target memory data using the second read voltage.

    Determining read voltages for memory systems with machine learning

    公开(公告)号:US11386972B2

    公开(公告)日:2022-07-12

    申请号:US17073800

    申请日:2020-10-19

    Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems with machine learning (ML) are provided. In one aspect, a memory system includes a memory and a memory controller configured to: obtain a first reading output of memory data using a first read voltage corresponding to a first set of parameters associated with the memory data; if the first reading output fails to pass an Error Correction Code (ECC) test, obtain a second reading output of the memory data using a second read voltage corresponding to a second set of parameters associated with the memory data and including the first set of parameters, the second read voltage being generated using at least one ML algorithm based on the second set of parameters; and if the second reading output passes the ECC test, output the second reading output as a target reading output of the memory data.

    DETERMINING READ VOLTAGES FOR MEMORY SYSTEMS

    公开(公告)号:US20220076762A1

    公开(公告)日:2022-03-10

    申请号:US17321933

    申请日:2021-05-17

    Abstract: Methods, devices, and systems for determining read voltages for memory systems are provided. In one aspect, a memory device includes an array of memory cells, an accumulating circuit, and a controller. Each of the memory cells is coupled to a corresponding word line of multiple word lines and a corresponding bit line of multiple bit lines. The accumulating circuit is configured to: when data stored in a page is read out by applying each of a plurality of read voltages on a word line corresponding to the page, accumulate read-out signals from multiple memory cells in the page to generate a respective output value that corresponds to the accumulated read-out signals for the read voltage. The controller is configured to determine a calibrated read voltage for the page based on the respective output values and the plurality of read voltages.

    DETERMINING READ VOLTAGES FOR MEMORY SYSTEMS WITH MACHINE LEARNING

    公开(公告)号:US20210241845A1

    公开(公告)日:2021-08-05

    申请号:US17073800

    申请日:2020-10-19

    Abstract: Systems, methods, and apparatus including computer-readable mediums for determining read voltages for memory systems with machine learning (ML) are provided. In one aspect, a memory system includes a memory and a memory controller configured to: obtain a first reading output of memory data using a first read voltage corresponding to a first set of parameters associated with the memory data; if the first reading output fails to pass an Error Correction Code (ECC) test, obtain a second reading output of the memory data using a second read voltage corresponding to a second set of parameters associated with the memory data and including the first set of parameters, the second read voltage being generated using at least one ML algorithm based on the second set of parameters; and if the second reading output passes the ECC test, output the second reading output as a target reading output of the memory data.

    Polar code generating method, and electronic device and non-transitory computer-readable storage medium therefor

    公开(公告)号:US10447436B2

    公开(公告)日:2019-10-15

    申请号:US15890500

    申请日:2018-02-07

    Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.

    Extended polar codes
    7.
    发明授权

    公开(公告)号:US10128982B2

    公开(公告)日:2018-11-13

    申请号:US15287120

    申请日:2016-10-06

    Abstract: A method for increasing coding reliability includes generating a generator matrix for an extended polar code including a standard polar code part and an additional frozen part. The standard polar code part has N bit-channels, including K information bit-channels and N−K frozen bit-channels. The additional frozen part has q additional frozen bit-channels. Among the K information bit-channels, q information bit-channels are re-polarized using the q additional frozen bit-channels. The method further includes receiving an input vector including K information bits and N+q−K frozen bits, and transforming, using the generator matrix, the input vector to an output vector including N+q encoded bits. The K information bits are allocated to the K information bit-channels, and the N+q−K frozen bits are allocated to the N−K frozen bit-channels and the q additional frozen bit-channels.

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