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    Memory device
    1.
    发明授权
    Memory device 有权

    公开(公告)号：US12238929B2

    公开(公告)日：2025-02-25

    申请号：US17349126

    申请日：2021-06-16

    Applicant: Kioxia Corporation

    Inventor： Mutsumi Okajima

    IPC: H10B43/30 ,  H10B43/10 ,  H10B43/20

    Abstract: A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film.

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US11665882B2

    公开(公告)日：2023-05-30

    申请号：US17012676

    申请日：2020-09-04

    Applicant: Kioxia Corporation

    Inventor： Masaharu Wada ,  Mutsumi Okajima ,  Tsuneo Inaba ,  Shinji Miyano

    IPC: H01L27/10 ,  H01L27/108 ,  G11C11/407

    CPC classification number: H01L27/10808 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10897 ,  G11C11/407

    Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US12052854B2

    公开(公告)日：2024-07-30

    申请号：US17466573

    申请日：2021-09-03

    Applicant: Kioxia Corporation

    Inventor： Mutsumi Okajima

    IPC: H10B12/00 ,  H01L21/02 ,  H01L29/24

    CPC classification number: H10B12/30 ,  H01L21/02565 ,  H01L29/24 ,  H10B12/03 ,  H10B12/05

    Abstract: A semiconductor memory device includes a plurality of memory portions arranged in a first direction, a plurality of semiconductor layers arranged in the first direction and electrically connected to the plurality of memory portions respectively, a plurality of gate electrodes arranged in the first direction and opposed to the plurality of semiconductor layers respectively, a gate insulating film disposed between the plurality of semiconductor layers and the plurality of gate electrodes, a first wiring extending in the first direction and connected to the plurality of gate electrodes, and a plurality of second wirings arranged in the first direction and connected to the plurality of semiconductor layers respectively. The plurality of semiconductor layers are opposed to surfaces on one side and the other side of each of the plurality of gate electrodes in the first direction via the gate insulating film.

    Memory device having multiple chips and method for manufacturing the same
    6.
    发明授权
    Memory device having multiple chips and method for manufacturing the same 有权

    公开(公告)号：US11387227B2

    公开(公告)日：2022-07-12

    申请号：US17017101

    申请日：2020-09-10

    Applicant: KIOXIA CORPORATION

    Inventor： Mutsumi Okajima

    IPC: H01L25/00 ,  H01L25/18 ,  H01L27/22 ,  H01L27/108 ,  H01L23/00 ,  H01L21/02 ,  G11C11/407 ,  G11C11/16

    Abstract: According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.

    Semiconductor memory device with a plurality of memory units
    9.
    发明授权
    Semiconductor memory device with a plurality of memory units 有权

    公开(公告)号：US11900986B2

    公开(公告)日：2024-02-13

    申请号：US17549262

    申请日：2021-12-13

    Applicant: Kioxia Corporation

    Inventor： Mutsumi Okajima ,  Mamoru Ishizaka

    IPC: G11C11/4091 ,  G11C5/02 ,  H01L23/48

    CPC classification number: G11C11/4091 ,  G11C5/025 ,  H01L23/481

    Abstract: A semiconductor memory device includes: memory units arranged in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the memory units; first gate electrodes arranged in the first direction and opposed to the first semiconductor layers; a first wiring extending in the first direction and connected to the first semiconductor layers; second wirings arranged in the first direction, and connected to the first gate electrodes; second semiconductor layers arranged in the first direction and disposed at first end portions of the second wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; third semiconductor layers arranged in the first direction and disposed at second end portions of the second wirings; and third gate electrodes arranged in the first direction and opposed to the third semiconductor layers.

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