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1.发明授权Method of repairing an integrated electronic circuit using a formed electrical isolation 有权使用形成的电隔离来修复集成电子电路的方法公开(公告)号：US07029927B2
公开(公告)日：2006-04-18
申请号：US10778323
申请日：2004-02-13
IPC分类号： H01L21/00
CPC分类号： H01L21/76807 , H01L21/76801 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.
摘要翻译： 修复由不正确的光刻掩模引起的集成电子电路中的缺陷的方法包括在电路的两个导电部分之间形成电隔离。 电隔离是通过用电绝缘材料至少部分地填充预先挖空的体积获得的，否则并且不正确地在两个导电部件之间形成电连接。 为此，在电路上形成具有露出掏空体积的孔径的掩模，以及用于引导电绝缘材料的填充的掩模和校正光刻限定的缺陷。
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公开(公告)号：US07521764B2
公开(公告)日：2009-04-21
申请号：US11142661
申请日：2005-06-01
IPC分类号： H01L29/76
CPC分类号： G11C17/16 , G11C11/5692 , Y10S257/903
摘要： A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.
摘要翻译： 一次性可编程双位存储器件包括具有半导体衬底的一个MOS存储晶体管，形成在衬底表面下方的第一和第二有源区被由形成沟道区的衬底的一部分分隔开，栅形成在 所述衬底的表面与沟道区域一致，并且其各自的远端分别与第一有源区域的一部分和第二有源区域的一部分对准，该栅极被永久地保持在地电位，并且 栅极氧化层在衬底的栅极和表面之间延伸。 门和第一有源区之间的完整或分解状态确定第一位的存储值，并且门和第二有源区之间的完整或分解状态确定第二位的存储值。
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公开(公告)号：US20050023617A1
公开(公告)日：2005-02-03
申请号：US10903527
申请日：2004-07-30
IPC分类号： H01L21/74 , H01L21/762 , H01L21/765 , H01L21/768 , H01L21/8244 , H01L23/485 , H01L23/528 , H01L23/535 , H01L27/11 , H01L29/78 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L21/743 , H01L21/76224 , H01L21/765 , H01L21/76802 , H01L21/76838 , H01L21/76895 , H01L23/485 , H01L23/5286 , H01L23/535 , H01L27/11 , H01L27/1104 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.
摘要翻译： 一种集成电路，包括半导体衬底，其中有源区域围绕或被填充有绝缘体的中空部围绕，并且其中导电区域嵌入至少一个中空的绝缘体中，所述导电区域连接到参考电压，并且 连接电路的至少一个相邻元件。
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4.发明授权Circuit indicating the phase relation between several signals having the same frequency 失效指示具有相同频率的若干信号之间的相位关系的电路
公开(公告)号：US5568072A
公开(公告)日：1996-10-22
申请号：US317132
申请日：1994-10-03
CPC分类号： G06F1/10 , G01R31/3016 , H03K5/26
摘要： A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input. Logic gates are respectively associated with each considered signal and are connected to indicate whether the considered signal is the first or the last activated signal when the flip-flops associated with all the pairs of signals including the considered signal are at respective suitable states once the first or last signal is activated.
摘要翻译： 指示在n个信号中激活的第一或最后信号的电路包括分别与信号对相关联的触发器，每对的第一信号被施加到触发器的复位输入，并且每对的第二信号为 应用于设定输入。 逻辑门分别与每个考虑的信号相关联，并且连接以指示当与包括所考虑的信号的所有信号对相关联的触发器在第一或第二激活信号处于相应的适当状态时，所考虑的信号是否是第一或最后激活的信号 或者最后一个信号被激活。
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公开(公告)号：US07453105B2
公开(公告)日：2008-11-18
申请号：US11478857
申请日：2006-06-30
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , G11C5/025 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including an assembly of functional blocks and an interconnection network formed of at least N levels of conductive tracks separated by conductive via levels, the interconnection network including a power supply network comprising a first assembly of substantially parallel rails placed at the N-th track level, and a second assembly of substantially parallel rails placed at the (N−1)-th track level under the first rail assembly, the rails of the first assembly being non-parallel to those of the second assembly, the power supply network further including, for each functional block, a third assembly of power supply rails placed at the (N−2)-th track level above the elements of the considered block, and in which the rails of the second assembly form an acute angle smaller than 80° with the rails of each third rail assembly.
摘要翻译： 一种集成电路，包括由导电通路层分开的至少N级的导电轨道形成的功能块组合和互连网络，所述互连网络包括电源网络，该电源网络包括放置在第N个 以及放置在第一导轨组件下方的第（N-1）个轨迹水平处的基本上平行的轨道的第二组件，第一组件的轨道与第二组件的轨道不平行，电源网络 对于每个功能块，进一步包括放置在所考虑的块的元件之上的第（N-2）个轨迹水平处的电源轨的第三组件，并且其中第二组件的轨道形成小于 80°，每个第三导轨组件的导轨。
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公开(公告)号：US20070076468A1
公开(公告)日：2007-04-05
申请号：US11541961
申请日：2006-10-02
IPC分类号： G11C11/00
CPC分类号： H01L27/11 , G11C7/20 , G11C11/412 , H01L27/1104
摘要： A random access memory cell includes a pair of complementary bit lines, a bistable circuit including first and second complementary read/write terminals, and two storage nodes. The first storage node is provided by a first nMos transistor and a first pMos transistor, and the second storage node is provided by a second nMos transistor and a second pMos transistor. A first switch transistor is connected between the first terminal and one of the lines of the bit line pair, and a second switch transistor is connected between the second terminal and the other line (BL) of the bit line pair. The two nMos transistors of the bistable circuit have different threshold voltages.
摘要翻译： 随机存取存储单元包括一对互补位线，包括第一和第二互补读/写终端的双稳态电路以及两个存储节点。 第一存储节点由第一nMOS晶体管和第一pMos晶体管提供，并且第二存储节点由第二nMOS晶体管和第二pMos晶体管提供。 第一开关晶体管连接在第一端子和位线对的一条线之间，第二开关晶体管连接在位线对的第二端子和另一线路（BL）之间。 双稳态电路的两个nMOS晶体管具有不同的阈值电压。
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7.发明申请公开(公告)号：US20060233015A1
公开(公告)日：2006-10-19
申请号：US11394873
申请日：2006-03-31
IPC分类号： G11C11/00
CPC分类号： G11C7/20 , G11C11/412 , Y10S257/901 , Y10S257/903
摘要： A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The two substrates can be biased with the first voltage. A clear flash controller flash clears the cells for temporarily bring the bias of the substrate of the NMOS transistor of the first CMOS inverter to the second voltage.
摘要翻译： 静态存储器件包括具有两个交叉耦合CMOS反相器的至少一个存储单元，以连接到第一和第二电压。 第一CMOS反相器的NMOS晶体管的衬底与第二CMOS反相器的NMOS晶体管的衬底电绝缘。 两个基板可以用第一电压偏置。 清除闪光灯控制器闪光灯清除单元，以暂时将第一CMOS反相器的NMOS晶体管的衬底的偏置带到第二电压。
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公开(公告)号：US20050281091A1
公开(公告)日：2005-12-22
申请号：US11157133
申请日：2005-06-20
IPC分类号： G11C8/16 , G11C11/413 , G11C7/10
CPC分类号： G11C8/16 , G11C11/413
摘要： A storage circuit using a dual-access memory, comprising means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access, at least two successive activations of said means controlling operations of the same type, reading or writing.
摘要翻译： 一种使用双重存取存储器的存储电路，包括用于以最大频率等于给定存取的激活的最大可能频率的两倍的方式交替地激活一个存取的装置，另一个存储装置，所述装置控制操作的至少两次连续激活 相同类型，阅读或写作。
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公开(公告)号：US06421293B1
公开(公告)日：2002-07-16
申请号：US09470897
申请日：1999-12-22
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C11/404 , G11C17/16 , H01L27/112 , H01L27/11206
摘要： An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.
摘要翻译： CMOS技术中的OTP存储单元，包括与不平衡编程晶体管串联的电容器，其漏极由比源更深和更少掺杂的区域制成。
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公开(公告)号：US5498983A
公开(公告)日：1996-03-12
申请号：US308080
申请日：1994-09-19
CPC分类号： H03K5/26 , G01R31/3016 , G01R31/31725
摘要： A device checks the skew between two clock signals among a plurality of clock signals having the same frequency. The two clock signals of each possible pair of clock signals respectively enable two successive flip-flops that are initially set at distinct states. The whole set of the flip-flops is connected in a looped shift register configuration. An alarm signal is provided by an Exclusive-OR gate receiving the outputs of two successive flip-flops of the shift register.
摘要翻译： 器件检查具有相同频率的多个时钟信号之间的两个时钟信号之间的偏斜。 每个可能的一对时钟信号的两个时钟信号分别使得两个连续的触发器最初被设置在不同的状态。 整组触发器以循环移位寄存器配置连接。 通过接收移位寄存器的两个连续触发器的输出的异或门提供报警信号。
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