-
公开(公告)号：US12052825B2
公开(公告)日：2024-07-30
申请号：US17355672
申请日：2021-06-23
发明人： Hongqing Zhang , Guoda Lian , Shidong Li , Junjun Li , Zhigang Song
摘要： A flexible circuit substrate that includes a conductive line on a flexible substrate and at least one slot in the conductive line on the flex substrate, where at one slot is in an area of the flexible circuit substrate that will be bent to prevent an open in the conductive line on the flexible substrate.
-
公开(公告)号：US10037895B2
公开(公告)日：2018-07-31
申请号：US14882548
申请日：2015-10-14
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert R. Robison
IPC分类号： H01L23/62 , H01L21/324 , H01L27/02 , H01L29/866 , H01L29/861
CPC分类号： H01L21/324 , H01L27/0255 , H01L29/8611 , H01L29/866
摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
-
公开(公告)号：US09881810B2
公开(公告)日：2018-01-30
申请号：US14154273
申请日：2014-01-14
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , Robert R. Robison
IPC分类号： H01L21/324 , H01L27/02 , H01L29/866 , H01L29/861
CPC分类号： H01L21/324 , H01L27/0255 , H01L29/8611 , H01L29/866
摘要： Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
-
公开(公告)号：US09331177B2
公开(公告)日：2016-05-03
申请号：US14529506
申请日：2014-10-31
发明人： Kangguo Cheng , Balasubramanian Pranatharthi Haran , Junjun Li , Shom Ponoth , Theodorus Eduardus Standaert , Tenko Yamashita
IPC分类号： H01L27/12 , H01L29/66 , H01L29/861 , H01L29/40 , H01L29/423 , H01L27/02 , H01L23/367 , H01L23/373 , H01L29/06
CPC分类号： H01L29/66795 , H01L23/367 , H01L23/3738 , H01L27/0255 , H01L27/1203 , H01L27/1211 , H01L29/0603 , H01L29/402 , H01L29/423 , H01L29/42376 , H01L29/6609 , H01L29/66742 , H01L29/861 , H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.
-
5.发明授权High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region 有权高电压横向双扩散金属氧化物半导体场效应晶体管（LDMOSFET）具有深的完全耗尽的漏极漂移区域公开(公告)号：US09059278B2
公开(公告)日：2015-06-16
申请号：US13959777
申请日：2013-08-06
发明人： John B. Campi, Jr. , Robert J. Gauthier, Jr. , Junjun Li , Rahul Mishra , Souvick Mitra , Mujahid Muhammad
CPC分类号： H01L27/0928 , H01L21/761 , H01L21/823814 , H01L21/823892 , H01L27/092 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0878 , H01L29/1045 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7801 , H01L29/7816 , H01L29/7835
摘要： Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate.
摘要翻译： 公开了半导体结构。 每个半导体结构可以包括衬底和在衬底上的至少一个横向双扩散金属氧化物半导体场效应晶体管（LDMOSFET）。 每个LDMOSFET可以具有完全耗尽的深漏极漂移区域（即完全耗尽的深度镇流电阻器区域），用于提供相对较高的阻塞电压。 公开了漏极漂移区域的不同配置，并且这些不同的配置也可以作为LDMOSFET的导电类型的函数而变化。 另外，每个半导体结构可以包括位于LDMOSFET下方的隔离带以及围绕LDMOSFET横向地定位并且垂直延伸到隔离带的隔离阱，使得LDMOSFET与衬底的下部分和任何相邻器件电隔离 底物。
-
公开(公告)号：US20150064856A1
公开(公告)日：2015-03-05
申请号：US14530034
申请日：2014-10-31
发明人： Kangguo Cheng , Balasubramanian Pranathari Haran , Junjun Li , Shom Ponoth , Theodrus Eduardus Standaert , Tenko Yamashita
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L23/367 , H01L23/3738 , H01L27/0255 , H01L27/1203 , H01L27/1211 , H01L29/0603 , H01L29/402 , H01L29/423 , H01L29/42376 , H01L29/6609 , H01L29/66742 , H01L29/861 , H01L29/8613 , H01L2924/0002 , H01L2924/00
摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.
摘要翻译： 提供用于集成电路的二极管和电阻。 深沟槽（DT）集成到二极管和电阻器中，用于热传导。 深沟槽促进热从绝缘体上半导体衬底传导到体衬底。 半导体散热片可形成为与深沟槽对齐。
-
公开(公告)号：US20150050784A1
公开(公告)日：2015-02-19
申请号：US14492622
申请日：2014-09-22
CPC分类号： H01L29/66386 , H01L27/0248 , H01L27/0262 , H01L29/66121 , H01L29/66371 , H01L29/7412 , H01L29/7416 , H01L29/87
摘要： Fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.
摘要翻译： 双向可控硅整流器件结构的制造方法。 第一导电类型的阱形成在器件区域中，其可以由绝缘体上半导体衬底的器件层限定。 在第一井中形成第一可控硅整流器的阳极。 在第一井中形成第二可控硅整流器的阴极。 第一可控硅整流器的阳极具有第一导电类型。 第二可控硅整流器的阴极具有与第一导电类型相反的第二导电类型。
-
公开(公告)号：US08951893B2
公开(公告)日：2015-02-10
申请号：US13733243
申请日：2013-01-03
发明人： John J. Ellis-Monaghan , Michael J. Hauser , Zhong-Xiang He , Junjun Li , Xuefeng Liu , Anthony K. Stamper
CPC分类号： B81C1/00301 , B81B7/007 , B81B2207/094 , B81C1/00246 , B81C2203/0714 , B81C2203/0742 , H01L21/84 , H01L27/1203
摘要： A semiconductor fabrication is described, wherein a MOS device and a MEMS device is fabricated simultaneously in the BEOL process. A silicon layer is deposited and etched to form a silicon film for a MOS device and a lower silicon sacrificial film for a MEMS device. A conductive layer is deposited atop the silicon layer and etched to form a metal gate and a first upper electrode. A dielectric layer is deposited atop the conductive layer and vias are formed in the dielectric layer. Another conductive layer is deposited atop the dielectric layer and etched to form a second upper electrode and three metal electrodes for the MOS device. Another silicon layer is deposited atop the other conductive layer and etched to form an upper silicon sacrificial film for the MEMS device. The upper and lower silicon sacrificial films are then removed via venting holes.
摘要翻译： 描述了半导体制造，其中在BEOL工艺中同时制造MOS器件和MEMS器件。 沉积并蚀刻硅层以形成用于MOS器件的硅膜和用于MEMS器件的下硅牺牲膜。 导电层沉积在硅层顶部并被蚀刻以形成金属栅极和第一上电极。 介电层沉积在导电层顶上，并且通孔形成在电介质层中。 另一个导电层沉积在电介质层顶上并被蚀刻以形成用于MOS器件的第二上电极和三个金属电极。 另一硅层沉积在另一导电层的顶上，并被蚀刻以形成用于MEMS器件的上硅牺牲膜。 然后通过排气孔去除上部和下部硅牺牲膜。
-
公开(公告)号：US08912625B2
公开(公告)日：2014-12-16
申请号：US14053986
申请日：2013-10-15
发明人： Michel J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam
CPC分类号： H01L27/0255 , G06F17/5022 , G06F17/5045 , H01L27/0262 , H01L27/1203 , H01L29/6609 , H01L29/66393 , H01L29/7436 , H01L29/861
摘要： Device structures with a reduced junction area in an SOI process, methods of making the device structures, and design structures for a lateral diode. The device structure includes one or more dielectric regions, such as STI regions, positioned in the device region and intersecting the p-n junction between an anode and cathode. The dielectric regions, which may be formed using shallow trench isolation techniques, function to reduce the width of a p-n junction with respect to the width area of the cathode at a location spaced laterally from the p-n junction and the anode. The width difference and presence of the dielectric regions creates an asymmetrical diode structure. The volume of the device region occupied by the dielectric regions is minimized to preserve the volume of the cathode and anode.
摘要翻译： 在SOI工艺中具有减小的结面积的器件结构，制造器件结构的方法以及横向二极管的设计结构。 器件结构包括位于器件区域中并与阳极和阴极之间的p-n结相交的一个或多个电介质区域，例如STI区域。 可以使用浅沟槽隔离技术形成的电介质区域用于在p-n结和阳极侧向间隔的位置处减小p-n结相对于阴极宽度区域的宽度。 介质区域的宽度差和存在产生不对称二极管结构。 由电介质区域占据的器件区域的体积被最小化以保持阴极和阳极的体积。
-
公开(公告)号：US20140342510A1
公开(公告)日：2014-11-20
申请号：US14450612
申请日：2014-08-04
IPC分类号： H01L21/8249 , H01L29/66 , H01L21/8234 , H01L27/02
CPC分类号： H01L21/8249 , H01L21/76224 , H01L21/823431 , H01L27/0251 , H01L27/0255 , H01L27/0262 , H01L27/0266 , H01L27/0629 , H01L27/0924 , H01L29/6609 , H01L29/66371 , H01L29/66795
摘要： Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.
摘要翻译： 本公开的方面提供了鳍状场效应晶体管（FinFET）工艺技术及其形成方法中的双重静电放电（ESD）保护器件。 在一个实施例中，双ESD保护器件包括：体硅衬底; 形成在本体硅衬底上的浅沟槽隔离（STI）区域; 位于STI区域上方的第一ESD器件; 以及位于所述STI区域下方的第二ESD器件，其中所述第一ESD器件在所述STI区域之上传导电流，并且所述第二ESD器件在所述STI区域之下传导电流。
-
-
-
-
-
-
-
-
-
搜索结果
84 条记录 (耗时 0.027 秒)
