公开(公告)号：US20050280088A1

公开(公告)日：2005-12-22

申请号：US10872025

申请日：2004-06-18

Applicant: Byoung Min ,  Scott Pozder ,  Hector Sanchez

Inventor： Byoung Min ,  Scott Pozder ,  Hector Sanchez

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/78615 ,  H01L21/743 ,  H01L21/76898 ,  H01L27/1203 ,  H01L29/78648

Abstract: A back side body contact for a transistor that extends through an opening in an insulating layer located adjacent to the backside of the body. The backside contact is coupled to an interconnect on the backside. In some examples, the interconnect is coupled to an interconnect located with respect the other side of an active layer which is coupled to a body voltage bias source.

Abstract translation: 用于晶体管的背侧体接触，其延伸穿过位于邻近身体背侧的绝缘层中的开口。 背面触点耦合到背面的互连。 在一些示例中，互连耦合到相对于耦合到体电压偏压源的有源层的另一侧定位的互连。

公开(公告)号：US20050275017A1

公开(公告)日：2005-12-15

申请号：US10856581

申请日：2004-05-28

Applicant: Scott Pozder ,  Salih Celik ,  Byoung Min ,  Vance Adams

Inventor： Scott Pozder ,  Salih Celik ,  Byoung Min ,  Vance Adams

IPC: H01L21/30 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/58 ,  H01L21/822 ,  H01L27/01 ,  H01L27/06 ,  H01L27/12 ,  H01L29/40

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L24/29 ,  H01L24/83 ,  H01L27/1203 ,  H01L29/7842 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/19043

Abstract: An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.

Abstract translation: 一种集成电路，其具有形成在第一晶片上的第一多个晶体管和形成在第二晶片上的第二多个晶体管。 第一晶体管的至少绝大部分晶体管是第一导电类型，并且第二多晶体管的至少绝大部分晶体管是第二导电类型。 在将晶片接合在一起之后，去除第二晶片的一部分，其中第二多个晶体管的通道的应变比第一多个晶体管的通道的应变更为压缩。

公开(公告)号：US20070267651A9

公开(公告)日：2007-11-22

申请号：US10075218

申请日：2002-02-14

Applicant: Thomas Kobayashi ,  Stephen Sheck ,  Scott Pozder

Inventor： Thomas Kobayashi ,  Stephen Sheck ,  Scott Pozder

IPC: H01L33/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract translation: 覆盖钝化层（35）并在封装材料（55,70）下方形成熔丝43。 在一个实施例中，在形成包装材料（55,70）之前吹过熔丝（43）。 在一些实施例中，熔丝（43）可以由金属（47），金属氮化物（42）或其组合形成。

公开(公告)号：US20070181653A1

公开(公告)日：2007-08-09

申请号：US11350306

申请日：2006-02-08

Applicant: Lynne Michaelson ,  Robert Jones ,  Scott Pozder

Inventor： Lynne Michaelson ,  Robert Jones ,  Scott Pozder

IPC: B23K31/02

CPC classification number: B23K37/047 ,  B23K2101/40 ,  H01L23/544 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/10165 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/757 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14

Abstract: Utilizing magnetic features located on different structures having semiconductor devices to align the structures when contacting the structures together. The magnetic features on each structure are of opposite polarity and provide magnetic forces for alignment of the structures. The magnetic forces can also be used to sense position and move the structures into an aligned position. In some examples, the structures include die with semiconductor devices. In one example, the structures are wafers with multiple die. In other examples, one of the structures is a die and the other is a wafer.

Abstract translation: 利用位于具有半导体器件的不同结构上的磁特征，以使结构在将结构接触在一起时对齐。 每个结构上的磁特征具有相反的极性，并提供用于对准结构的磁力。 磁力也可用于检测位置并将结构移动到对准位置。 在一些示例中，结构包括具有半导体器件的管芯。 在一个示例中，结构是具有多个管芯的晶片。 在其他示例中，其中一个结构是模具，另一个是晶片。

公开(公告)号：US20070057384A1

公开(公告)日：2007-03-15

申请号：US11226025

申请日：2005-09-14

Applicant: Syed Alam ,  Robert Jones ,  Scott Pozder

Inventor： Syed Alam ,  Robert Jones ,  Scott Pozder

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541

Abstract: A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Abstract translation: 互易设计对称性允许晶片上的堆叠晶片或晶片使用仅仅几层（例如，金属互连层）变化的相同设计或设计。 翻转或旋转一个模具或晶片允许堆叠的模具相对于彼此具有相互的取向，其可用于减小垂直堆叠的模具和/或晶片之间所需的互连。 当晶片和/或管芯堆叠时，翻转和/或旋转也可用于改善散热。 然后可以包装堆叠的晶片或管芯。

公开(公告)号：US20050285259A1

公开(公告)日：2005-12-29

申请号：US11215374

申请日：2005-08-26

Applicant: Scott Pozder ,  Michelle Rasco

Inventor： Scott Pozder ,  Michelle Rasco

IPC: G11C11/16 ,  H01L20060101 ,  H01L21/44 ,  H01L21/58 ,  H01L21/60 ,  H01L23/06 ,  H01L23/10 ,  H01L23/14 ,  H01L23/48 ,  H01L23/552

CPC classification number: H01L23/552 ,  G11C11/16 ,  H01L23/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/29499 ,  H01L2224/73253 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

公开(公告)号：US20050104193A1

公开(公告)日：2005-05-19

申请号：US10716655

申请日：2003-11-19

Applicant: Scott Pozder ,  Michelle Rasco

Inventor： Scott Pozder ,  Michelle Rasco

IPC: G11C11/16 ,  H01L20060101 ,  H01L21/44 ,  H01L21/58 ,  H01L21/60 ,  H01L23/06 ,  H01L23/10 ,  H01L23/14 ,  H01L23/48 ,  H01L23/552

CPC classification number: H01L23/552 ,  G11C11/16 ,  H01L23/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/29499 ,  H01L2224/73253 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

公开(公告)号：US20070023121A1

公开(公告)日：2007-02-01

申请号：US11193926

申请日：2005-07-29

Applicant: Robert Jones ,  Scott Pozder

Inventor： Robert Jones ,  Scott Pozder

IPC: B32B37/00 ,  B32B38/04 ,  H01L21/30

CPC classification number: H01L21/50 ,  B32B37/00 ,  H01L22/20 ,  Y10T156/10 ,  Y10T156/1052 ,  Y10T156/1062

Abstract: A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

Abstract translation: 组装电子设备的方法包括测试第一晶片的第一晶片以识别功能第一裸片的位置并将第一晶片分成一组面板，其中面板包括第一裸片的MxN阵列。 面板结合到第二晶片的面板部位以形成面板堆叠，其中面板部位在第二晶片中限定第二模具的MxN阵列。 面板堆叠被锯成包括结合到第二模具的第一模具的装置。 可以将第一晶片划分成面板可以静态或动态地进行（以最大化具有超过特定阈值的产量的面板的数量）。 可以执行根据功能性模具图案的面板和面板位置的分层以优先地将面板粘合到同一箱的面板位置。

公开(公告)号：US20050014356A1

公开(公告)日：2005-01-20

申请号：US10910036

申请日：2004-08-03

Applicant: Scott Pozder ,  Thomas Kobayashi

Inventor： Scott Pozder ,  Thomas Kobayashi

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/48 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad (134) that is formed over a semiconductor substrate (100). A dielectric layer (136) is then formed over the conductive bond pad (134). Portions of the dielectric layer (136) are removed such that the dielectric layer (136) becomes perforated and a portion of the conductive bond pad (134) is exposed. Remaining portions of the dielectric layer (136) form support structures (138) that overlie that bond pad. A self-passivating conductive capping layer (204) is then formed overlying the bond pad structure, where the perforations in the dielectric layer (136) allow for electrical contact between the capping layer (204) and the exposed portions of the underlying bond pad (134). The support structures (138) provide a mechanical barrier that protects the interface between the capping layer (204) and the bond pad (134). Additional mechanical robustness is achieved when the support structures (138) remain coupled to the unremoved portion of the dielectric layer (136), as forces buffered by the support structures (138) are distributed across the dielectric layer (136) and not concentrated at the bond pad location.

Abstract translation: 提出了一种能够在探测或包装操作期间施加的外力抵抗的复合焊盘。 复合接合焊盘包括形成在半导体衬底（100）上的非自钝化导电接合焊盘（134）。 然后在导电接合焊盘（134）之上形成电介质层（136）。 去除电介质层（136）的部分，使得电介质层（136）变得穿孔并且导电接合焊盘（134）的一部分被暴露。 电介质层（136）的剩余部分形成覆盖该接合焊盘的支撑结构（138）。 然后，形成覆盖接合焊盘结构的自钝化导电覆盖层（204），其中电介质层（136）中的穿孔允许封盖层（204）和下焊接垫（204）的暴露部分之间的电接触 134）。 支撑结构（138）提供了保护覆盖层（204）和接合焊盘（134）之间的界面的机械屏障。 当支撑结构（138）保持耦合到电介质层（136）的未移动部分时，由支撑结构（138）缓冲的力分布在电介质层（136）上并且不集中在电介质层 键盘位置。

公开(公告)号：US20070231950A1

公开(公告)日：2007-10-04

申请号：US11278042

申请日：2006-03-30

Applicant: Scott Pozder ,  Lynne Michaelson ,  Varughese Mathew

Inventor： Scott Pozder ,  Lynne Michaelson ,  Varughese Mathew

IPC: H01L21/00

CPC classification number: H01L21/76898 ,  H01L21/76805 ,  H01L23/481 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Abstract translation: 一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。 第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。 该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合 层到着陆垫，并用导电填充材料填充开口。 选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。