公开(公告)号：US20070231950A1

公开(公告)日：2007-10-04

申请号：US11278042

申请日：2006-03-30

申请人： Scott Pozder ,  Lynne Michaelson ,  Varughese Mathew

发明人： Scott Pozder ,  Lynne Michaelson ,  Varughese Mathew

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/76805 ,  H01L23/481 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

摘要： A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

摘要翻译： 一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。 第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。 该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合 层到着陆垫，并用导电填充材料填充开口。 选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。

公开(公告)号：US20060270234A1

公开(公告)日：2006-11-30

申请号：US11140162

申请日：2005-05-27

申请人： Varughese Mathew ,  Edward Acosta ,  Sam Garcia ,  Lynne Michaelson

发明人： Varughese Mathew ,  Edward Acosta ,  Sam Garcia ,  Lynne Michaelson

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76849 ,  C11D3/2082 ,  C11D3/2086 ,  C11D3/3947 ,  C11D11/0047 ,  H01L21/02074

摘要： A method for making a semiconductor device includes cleaning a semiconductor wafer after a chemical mechanical polishing (CMP) process to remove or reduce particles of copper, a corrosion inhibitor such as triazole, and a copper oxide layer on the copper layer. In order to prepare for plating the copper layer with a layer that functions as a barrier to copper migration or diffusion, the surface of the copper layer and the dielectric layer are treated with an oxidant, a surfactant, and copper-chelating agent. The copper-chelating is preferably a mild acid such as an organic acid. The oxidant is particularly useful in removing the corrosion inhibitor. The barrier layer, preferably conductive, is then plated on the surface of the copper layer. Subsequent interlayer dielectric layers and copper layers follow that can use the same process.

摘要翻译： 制造半导体器件的方法包括在化学机械抛光（CMP）工艺之后清洗半导体晶片，以去除或减少铜的颗粒，诸如三唑的腐蚀抑制剂和铜层上的氧化铜层。 为了准备用作为阻挡铜迁移或扩散的层的铜层的电镀，铜层和电介质层的表面用氧化剂，表面活性剂和铜螯合剂处理。 铜螯合物优选为弱酸，例如有机酸。 氧化剂特别适用于去除腐蚀抑制剂。 然后将优选导电的阻挡层电镀在铜层的表面上。 随后的层间电介质层和铜层可以使用相同的工艺。

公开(公告)号：US20060202339A1

公开(公告)日：2006-09-14

申请号：US11078236

申请日：2005-03-11

申请人： Lynne Michaelson ,  Edward Acosta ,  Ritwik Chatterjee ,  Stanley Filipiak ,  Sam Garcia ,  Varughese Mathew

发明人： Lynne Michaelson ,  Edward Acosta ,  Ritwik Chatterjee ,  Stanley Filipiak ,  Sam Garcia ,  Varughese Mathew

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76822 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76856

摘要： A diffusion barrier stack is formed by forming a layer comprising a metal over a conductor that includes copper; and forming a first dielectric layer over the layer, wherein the dielectric layer is of a thickness that alone it can not serve as a diffusion barrier layer to the conductor and the first dielectric layer prevents oxidation of the layer. In one embodiment, the diffusion barrier stack includes two layers; the first layer is a conductive layer and the second layer is a dielectric layer. The diffusion barrier stack minimizes electromigration and copper diffusion from the conductor.

摘要翻译： 通过在包括铜的导体上形成包括金属的层来形成扩散阻挡叠层; 以及在所述层上形成第一电介质层，其中所述电介质层的厚度单独地不能用作所述导体的扩散阻挡层，并且所述第一介电层防止所述层的氧化。 在一个实施例中，扩散阻挡堆叠包括两层; 第一层是导电层，第二层是电介质层。 扩散阻挡层将导电体的电迁移和铜扩散最小化。

公开(公告)号：US09117756B2

公开(公告)日：2015-08-25

申请号：US13361171

申请日：2012-01-30

申请人： Varughese Mathew

发明人： Varughese Mathew

IPC分类号： H01L23/29 ,  H01L23/28 ,  H01L23/00 ,  C08K5/09

CPC分类号： H01L23/293 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/48463 ,  H01L2924/181 ,  H01L2924/00

摘要： A packaged electronic device including an electronic device, a conductive structure, and an encapsulant. The encapsulant has chlorides and a negatively-charged corrosion inhibitor for preventing corrosion of the conductive structure.

摘要翻译： 包括电子器件，导电结构和密封剂的封装电子器件。 密封剂具有氯化物和带负电荷的腐蚀抑制剂，用于防止导电结构的腐蚀。

公开(公告)号：US07932175B2

公开(公告)日：2011-04-26

申请号：US11807745

申请日：2007-05-29

申请人： Ritwik Chatterjee ,  Eddie Acosta ,  Sam S. Garcia ,  Varughese Mathew

发明人： Ritwik Chatterjee ,  Eddie Acosta ,  Sam S. Garcia ,  Varughese Mathew

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898

摘要： A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

摘要翻译： 一种用于形成通孔的方法，包括（a）提供包括设置在半导体衬底（203）上的掩模（210）的结构，其中所述结构具有限定在其中的开口（215），所述开口延伸穿过所述掩模并进入所述衬底， 并且其中所述掩模包括第一导电层; （b）沉积第二导电层（219），使得所述第二导电层与所述第一导电层电接触，所述第二导电层具有在所述开口的表面上延伸的第一部分，所述第二部分延伸 在面罩的与开口相邻的一部分上方; （c）去除第二导电层的第二部分; 和（d）在第二导电层的第一部分上沉积第一金属（221）。

公开(公告)号：US20080299762A1

公开(公告)日：2008-12-04

申请号：US11807777

申请日：2007-05-29

申请人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

发明人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898

摘要： A method for forming an interconnect, comprising (a) providing a substrate (203) with a via (205) defined therein; (b) forming a seed layer (211) such that a first portion of the seed layer extends over a surface of the via, and a second portion of the seed layer extends over a portion of the substrate; (c) removing the second portion of the seed layer; and (d) depositing a metal (215) over the first portion of the seed layer by an electroless process.

摘要翻译： 一种用于形成互连的方法，包括：（a）提供具有在其中限定的通孔（205）的衬底（203）; （b）形成晶种层（211），使种子层的第一部分在通孔的表面上延伸，种子层的第二部分延伸到衬底的一部分上; （c）去除种子层的第二部分; 和（d）通过无电解方法在种子层的第一部分上沉积金属（215）。

公开(公告)号：US20070049008A1

公开(公告)日：2007-03-01

申请号：US11215375

申请日：2005-08-26

申请人： Gerald Martin ,  Sam Garcia ,  Varughese Mathew

发明人： Gerald Martin ,  Sam Garcia ,  Varughese Mathew

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/7684

摘要： A method for making a semiconductor device includes forming a patterned dielectric overlying active circuitry, the patterned dielectric having a plurality of cavities. A diffusion barrier is formed over the patterned dielectric. A conductive layer is formed over the diffusion barrier in the plurality of cavities. The conductive layer is etched back to be below a top surface of the dielectric, forming recessed areas over the conductive layers in the plurality of cavities. The recessed areas are then filled with a capping film. The capping film and the diffusion barrier are removed to provide a relatively smooth planarized surface. Providing a relatively smooth planarized surface reduces leakage currents between conductors.

摘要翻译： 制造半导体器件的方法包括形成覆盖有源电路的图案化电介质，所述图案化电介质具有多个空腔。 在图案化电介质上形成扩散阻挡层。 在多个空腔中的扩散阻挡层上形成导电层。 导电层被回蚀刻到电介质的顶表面之下，在多个空腔中的导电层上形成凹陷区域。 然后用封盖膜填充凹进的区域。 去除覆盖膜和扩散阻挡层以提供相对光滑的平坦化表面。 提供相对平滑的平坦化表面减少导体之间的漏电流。

公开(公告)号：US07807572B2

公开(公告)日：2010-10-05

申请号：US11969368

申请日：2008-01-04

申请人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

发明人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

摘要翻译： 一种方法形成微型至第一半导体器件的外部接触。 在外部触点上形成铜钉。 螺柱在第一半导体器件的表面之上延伸。 将铜柱浸入锡溶液中。 锡替代至少95％的螺柱铜，优选超过99％。 结果是具有小于5重量％铜的锡微粉末。 由于微电极基本上是纯锡，所以在第一半导体器件的微型焊盘未被接合的时间内，金属间键不会形成。 因为不形成金属间键，因此产生较小的微尺寸尺寸。 当第一半导体器件结合到上覆的第二半导体器件时，焊接尺寸不会显着增加堆叠芯片的高度。

公开(公告)号：US20090176366A1

公开(公告)日：2009-07-09

申请号：US11969368

申请日：2008-01-04

申请人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

发明人： Varughese Mathew ,  Eddie Acosta ,  Ritwik Chatterjee ,  Sam S. Garcia

IPC分类号： H01L21/288

CPC分类号： H01L24/11 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014

摘要： A method forms a micropad to an external contact of a first semiconductor device. A stud of copper is formed over the external contact. The stud extends above a surface of the first semiconductor device. The stud of copper is immersed in a solution of tin. The tin replaces at least 95 percent of the copper of the stud and preferably more than 99 percent. The result is a tin micropad that has less than 5 percent copper by weight. Since the micropad is substantially pure tin, intermetallic bonds will not form during the time while the micropads of the first semiconductor device are not bonded. Smaller micropad dimensions result since intermetallic bonds do not form. When the first semiconductor device is bonded to an overlying second semiconductor device, the bond dimensions do not significantly increase the height of stacked chips.

摘要翻译： 一种方法形成微型至第一半导体器件的外部接触。 在外部触点上形成铜钉。 螺柱在第一半导体器件的表面之上延伸。 将铜柱浸入锡溶液中。 锡替代至少95％的螺柱铜，优选超过99％。 结果是具有小于5重量％铜的锡微粉末。 由于微电极基本上是纯锡，所以在第一半导体器件的微型焊盘未被接合的时间内，金属间键不会形成。 因为不形成金属间键，因此产生较小的微尺寸尺寸。 当第一半导体器件结合到上覆的第二半导体器件时，焊接尺寸不会显着增加堆叠芯片的高度。

公开(公告)号：US07378339B2

公开(公告)日：2008-05-27

申请号：US11278042

申请日：2006-03-30

申请人： Scott K. Pozder ,  Lynne M. Michaelson ,  Varughese Mathew

发明人： Scott K. Pozder ,  Lynne M. Michaelson ,  Varughese Mathew

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L21/76805 ,  H01L23/481 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/00

摘要： A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

摘要翻译： 一种形成半导体器件的方法包括提供具有着陆焊盘的第一集成电路，并且使用至少一个接合层将第二集成电路附接到第一集成电路。 第二集成电路具有电路间迹线，电路间迹线具有电路间迹线开口。 该方法还包括形成通过第二集成电路的开口，该开口延伸穿过该电路间开口，在该开口中的该电路间的迹线的暴露部分上形成选择性屏障，该开口通过该至少一个接合 层到着陆垫，并用导电填充材料填充开口。 选择性阻挡层包括钴或镍中的至少一种，并且导电填充材料电连接电路间迹线和着陆焊盘。