公开(公告)号：US20230163013A1

公开(公告)日：2023-05-25

申请号：US18090471

申请日：2022-12-28

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Akhila Mallavarapu ,  Crystal Barrera

IPC: H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687 ,  H01L23/544 ,  H01L27/06

CPC classification number: H01L21/6833 ,  H01L21/3065 ,  H01L21/6838 ,  H01L21/67069 ,  H01L21/68721 ,  H01L21/67259 ,  H01L21/6836 ,  H01L23/544 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2223/54426

Abstract: A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

公开(公告)号：US11469131B2

公开(公告)日：2022-10-11

申请号：US16472766

申请日：2017-12-22

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Mark McDermott ,  Shrawan Singhal ,  Ovadia Abed ,  Lawrence Dunn ,  Vipul Goyal ,  Michael Cullinan

IPC: H01L21/683 ,  G06F30/392 ,  G06F30/398 ,  G06F30/396 ,  B81C99/00 ,  H01L23/544 ,  G06F117/10

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

公开(公告)号：US20220270930A1

公开(公告)日：2022-08-25

申请号：US17735476

申请日：2022-05-03

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Akhila Mallavarapu ,  Jaydeep Kulkarni ,  Michael Watts ,  Sanjay Banerjee

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L21/3065 ,  H01L29/423 ,  H01L21/306

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.

公开(公告)号：US20210389666A1

公开(公告)日：2021-12-16

申请号：US16322882

申请日：2017-08-03

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Shrawan Singhal ,  Ovadia Abed ,  Lawrence Dunn

IPC: G03F7/00 ,  G01Q60/24

Abstract: A method for fabricating patterns. An inverse optimization scheme is implemented to determine process parameters used to obtain a desired film thickness of a liquid resist formulation, where the liquid resist formulation includes a solvent and one or more non-solvent components. A substrate is covered with a substantially continuous film of the liquid resist formulation using one or more of the following techniques: dispensing discrete drops of a diluted monomer on the substrate using an inkjet and allowing the dispensed drops to spontaneously spread and merge, slot die coating and spin-coating. The liquid resist formulation is diluted in the solvent. The solvent is then substantially evaporated from the liquid resist formulation forming a film. A gap between a template and the substrate is then closed. The film is cured to polymerize the film and the substrate is separated from the template leaving the polymerized film on the substrate.

公开(公告)号：US20210366771A1

公开(公告)日：2021-11-25

申请号：US16957046

申请日：2018-12-21

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Ovadia Abed ,  Mark McDermott ,  Jaydeep Kulkarni ,  Shrawan Singhal

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L23/544 ,  H01L27/06 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

公开(公告)号：US20210134640A1

公开(公告)日：2021-05-06

申请号：US16472766

申请日：2017-12-22

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Aseem Sayal ,  Mark McDermott ,  Shrawan Singhal ,  Ovadia Abed ,  Lawrence Dunn ,  Vipul Goyal ,  Michael Cullinan

IPC: H01L21/683 ,  B81C99/00 ,  G06F30/398 ,  G06F30/396 ,  G06F30/392 ,  H01L23/544

Abstract: A method for assembling heterogeneous components. The assembly process includes using a vacuum based pickup mechanism in conjunction with sub-nm precise more alignment techniques resulting in highly accurate, parallel assembly of feedstocks.

公开(公告)号：US09941389B2

公开(公告)日：2018-04-10

申请号：US15133007

申请日：2016-04-19

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Praveen Joseph ,  Ovadia Abed ,  Michelle Grigas ,  Akhila Mallavarapu ,  Paras Ajay

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  G03F7/00 ,  G02B6/124 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L29/6659 ,  G02B6/124 ,  G03F7/0002 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/0271 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224 ,  H01L28/90 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545

Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

公开(公告)号：US20160118249A1

公开(公告)日：2016-04-28

申请号：US14921866

申请日：2015-10-23

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Anshuman Cherala ,  Meghali Chopra ,  Roger Bonnecaze ,  Ovadia Abed ,  Bailey Yin ,  Akhila Mallavarapu ,  Shrawan Singhal ,  Brian Gawlik

IPC: H01L21/02

CPC classification number: H01L21/02521 ,  B81C1/00031 ,  B81C2201/0187 ,  B82Y40/00 ,  G03F7/0002 ,  G11B5/746 ,  H01L21/02381 ,  H01L21/02617 ,  H01L21/3086 ,  H01L29/945 ,  Y10S977/887 ,  Y10S977/888 ,  Y10S977/89

Abstract: A method for template fabrication of ultra-precise nanoscale shapes. Structures with a smooth shape (e.g., circular cross-section pillars) are formed on a substrate using electron beam lithography. The structures are subject to an atomic layer deposition of a dielectric interleaved with a deposition of a conductive film leading to nanoscale sharp shapes with features that exceed electron beam resolution capability of sub-10 nm resolution. A resist imprint of the nanoscale sharp shapes is performed using J-FIL. The nanoscale sharp shapes are etched into underlying functional films on the substrate forming a nansohaped template with nanoscale sharp shapes that include sharp corners and/or ultra-small gaps. In this manner, sharp shapes can be retained at the nanoscale level. Furthermore, in this manner, imprint based shape control for novel shapes beyond elementary nanoscale structures, such as dots and lines, can occur at the nanoscale level.

Abstract translation: 一种超精密纳米尺寸模板制作方法。 使用电子束光刻在基板上形成具有平滑形状（例如圆形横截面支柱）的结构。 这些结构受到与导电膜沉积物交替的介电质的原子层沉积，导致具有超过10nm分辨率的电子束分辨能力的特征的纳米级锐利形状。 使用J-FIL进行纳米级锐利形状的抗蚀刻印刷。 将纳米级尖锐形状蚀刻到基底上的下面的功能膜中，形成具有包括尖角和/或超小间隙的纳米尖锐形状的纳米成形模板。 以这种方式，尖锐的形状可以保持在纳米级。 此外，以这种方式，可以在纳米尺度上发生基本的纳米尺度结构（例如点和线）之外的新颖形状的基于压印的形状控制。

公开(公告)号：US20150048050A1

公开(公告)日：2015-02-19

申请号：US14462198

申请日：2014-08-18

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Shrawan Singhal

IPC: B05D1/40 ,  B05D1/34 ,  B05D1/42 ,  B05D5/00 ,  B05D1/02 ,  B05D3/12 ,  B05D3/06 ,  B05D3/00

CPC classification number: B05D1/40 ,  B05D1/02 ,  B05D1/34 ,  B05D1/42 ,  B05D3/007 ,  B05D3/0254 ,  B05D3/0466 ,  B05D3/0486 ,  B05D3/0493 ,  B05D3/067 ,  B05D3/12 ,  B05D5/00 ,  B29C35/0888 ,  B29C43/021 ,  B29C59/026 ,  B81C1/0046 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/0271

Abstract: An inkjet-based process for programmable deposition of thin films of a user-defined profile. Drops of a pre-cursor liquid organic material are dispensed at various locations on a substrate by a multi-jet. A superstrate that has been bowed due to a backside pressure is brought down such that a first contact of the drops is made by a front side of the superstrate thereby initiating a liquid front that spreads outward merging with the drops to form a contiguous film captured between the substrate and the superstrate. A non-equilibrium transient state of the superstrate, the contiguous film and the substrate then occurs after a duration of time. The contiguous film is then cured to crosslink it into a polymer. The superstrate is then separated from the polymer thereby leaving a polymer film on the substrate. In such a manner, non-uniform films can be formed without significant material wastage in an inexpensive manner.

Abstract translation: 用于用户定义的轮廓的薄膜的可编程沉积的基于喷墨的方法。 通过多射流将预取液体有机材料的液滴分配在基板上的各个位置。 已经由于背侧压力而被鞠躬的顶板被降低，使得液滴的第一次接触由顶板的前侧制成，从而引发液面向外扩散，与液滴向外汇合形成连续的薄膜， 底物和底层。 然后在持续时间之后发生上层的非平衡过渡状态，连续膜和衬底。 然后将连续的膜固化以将其交联成聚合物。 然后将上层与聚合物分离，从而在基材上留下聚合物膜。 以这种方式，可以以廉价的方式形成不均匀的膜，而不会显着的材料浪费。

公开(公告)号：US20240395578A1

公开(公告)日：2024-11-28

申请号：US18696620

申请日：2022-09-30

Applicant: Board of Regents, The University of Texas System

Inventor： Sidlgata V. Sreenivasan ,  Paras Ajay ,  Austin Anthis

IPC: H01L21/67 ,  B05B17/06 ,  B41J3/407

Abstract: A system for assembling a first substrate to a second substrate. One or more deformable substrate chucks are utilized to match a topography of a bonding surface on the first substrate to a topography of a bonding surface on the second substrate, where a volatile lubricant is utilized during an alignment step.