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    Precharge circuitry in RAM circuit
    1.
    发明授权
    Precharge circuitry in RAM circuit 有权
    RAM电路中的预充电电路

    公开(公告)号：US6097651A

    公开(公告)日：2000-08-01

    申请号：US345971

    申请日：1999-06-30

    Applicant: Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

    Inventor： Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

    IPC: G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/00

    CPC classification number: G11C11/417 ,  G11C7/1045 ,  G11C7/12

    Abstract: A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

    Abstract translation: 随机存取存储器（RAM）装置包括存储器单元中的缓冲器，以将锁存电路与读位线隔离。 因此，避免了由读取位线上的电容性负载引起的读取干扰错误。 此外，对于写位线的预充电要求被简化，因为缓冲器允许存储单元中的锁存电路的优化。 RAM装置包括在执行写入操作之前将写入位线预充电到接地参考电压的预充电电路。 通过将写位线预充电到接地参考电压，避免了由写位线上的电容负载引起的写干扰问题。 此外，通过将写入位线耦合到接地参考电压，通过对写入位线进行预充电，很少或没有电力消耗。

    Serializer/deserializer embedded in a programmable device
    2.
    发明授权
    Serializer/deserializer embedded in a programmable device 有权
    串行器/解串器嵌入可编程器件

    公开(公告)号：US06542096B2

    公开(公告)日：2003-04-01

    申请号：US09939533

    申请日：2001-08-24

    Applicant: Andrew K. Chan ,  James M. Apland ,  Senani Gunaratna ,  SunilKumar G. Mudunuri ,  Ket-Chong Yap

    Inventor： Andrew K. Chan ,  James M. Apland ,  Senani Gunaratna ,  SunilKumar G. Mudunuri ,  Ket-Chong Yap

    IPC: H03M900

    CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/22 ,  H04J3/0685 ,  H04L7/0008 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/10

    Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

    Abstract translation: 根据本发明，现场可编程门阵列的串行器/解串器核心包括通道时钟和数据通道。 数据通道可以在两种模式下对数据进行序列化和反序列化。 在第一模式中，从数据中恢复嵌入的时钟信号。 在第二模式中，时钟信号由通道时钟提供。 选择信号确定串行器/解串器核心中的每个数据信道在哪种模式下操作。 阶梯式时钟发生器产生一系列用于串行化和反序列化数据的上升沿信号。 串行化和反序列化的位数由控制信号确定到楼梯级时钟发生器中的一组多路复用器，确定楼梯级时钟发生器中有多少个寄存器被激活。

    Programmable antifuse interfacing a programmable logic and a dedicated device
    3.
    发明授权
    Programmable antifuse interfacing a programmable logic and a dedicated device 有权
    可编程反熔丝接口可编程逻辑和专用器件

    公开(公告)号：US06552410B1

    公开(公告)日：2003-04-22

    申请号：US09650773

    申请日：2000-08-29

    Applicant: David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

    Inventor： David D. Eaton ,  Ket-Chong Yap ,  Kevin K. Yee ,  E. Thomas Hart ,  Andrew K. Chan ,  Neal A. Palmer ,  Michael W. Dini ,  James Apland ,  Panawalge S. N. Gunaratna

    IPC: H01L2200

    CPC classification number: H03K19/1776 ,  H03K19/17732 ,  H03K19/17744

    Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers. The path of the test signal through the JTAG registers is selectable to pass around the periphery of both the programmable and dedicated devices or through the interface and around the periphery of only one of the programmable and dedicated devices.

    Abstract translation: 诸如现场可编程门阵列的可编程电路以及诸如ASIC类型器件的专用器件在单个集成电路上与基于反熔丝的接口耦合在一起。 与专用设备通信的可配置非易失性存储器也位于集成电路上。 可编程电路的平台是现有可编程电路的一半，无需设计可编程电路。 可编程电路包括时钟网络，其从时钟端子以及专用器件中的时钟网络接收时钟信号。 专用器件和可编程电路之间的接口包括具有带测试电路的缓冲器的多个导体。 测试电路包括PMOS测试晶体管和NMOS测试晶体管，其允许对缓冲器进行测试而不编程耦合到导体的反熔丝。 使用JTAG寄存器测试周边和可编程电路与专用设备之间的接口中的输入/输出端子。 通过JTAG寄存器的测试信号的路径可选择通过可编程和专用设备的周边，或通过接口和仅可编程和专用设备之一的外围环绕。

    Power-up circuit for field programmable gate arrays
    4.
    发明授权
    Power-up circuit for field programmable gate arrays 失效
    现场可编程门阵列的上电电路

    公开(公告)号：US06101074A

    公开(公告)日：2000-08-08

    申请号：US94462

    申请日：1998-06-10

    Applicant: James M. Apland ,  Andrew K. Chan

    Inventor： James M. Apland ,  Andrew K. Chan

    IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

    CPC classification number: H03K17/223 ,  H03K19/17772 ,  H03K19/17784

    Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

    Abstract translation: 保护电路在门阵列加电期间防止现场可编程门阵列中的逻辑模块中的电流尖峰。 保护电路在上电期间将电压提供给逻辑模块的内部禁止输入，直到由电荷泵输出的电压达到预定电压。 内部禁用输入端的电压关闭逻辑模块中的晶体管，并防止电流尖峰。 当电荷泵输出的电压达到预定电压时，保护电路不再将电压提供给逻辑模块的内部禁止输入。

    Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array
    5.
    发明授权
    Security antifuse that prevents readout of some but not other information from a programmed field programmable gate array 失效
    防止从编程的现场可编程门阵列读出一些而不是其他信息的安全反熔丝

    公开(公告)号：US5898776A

    公开(公告)日：1999-04-27

    申请号：US754461

    申请日：1996-11-21

    Applicant: James M. Apland ,  David D. Eaton ,  Andrew K. Chan

    Inventor： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

    IPC: G01R31/317 ,  G01R31/3185 ,  H04L9/00

    CPC classification number: G01R31/318519 ,  G01R31/31719 ,  G01R31/318555 ,  G01R31/31702 ,  G01R31/318558

    Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

    Abstract translation: 现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。 在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用， 。 还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。 因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。 提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

    Power-up circuit for field programmable gate arrays
    6.
    发明授权
    Power-up circuit for field programmable gate arrays 失效

    公开(公告)号：US5828538A

    公开(公告)日：1998-10-27

    申请号：US775984

    申请日：1997-01-03

    Applicant: James M. Apland ,  Andrew K. Chan

    Inventor： James M. Apland ,  Andrew K. Chan

    IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

    CPC classification number: H03K17/223 ,  H03K19/17772 ,  H03K19/17784

    Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

    ASIC having dense mask-programmable portion and related system development method
    7.
    发明授权
    ASIC having dense mask-programmable portion and related system development method 失效
    ASIC具有密集的可编程部分和相关的系统开发方法

    公开(公告)号：US07346876B2

    公开(公告)日：2008-03-18

    申请号：US10944323

    申请日：2004-09-17

    Applicant: Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

    Inventor： Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

    IPC: G06F17/50 ,  G06F19/00 ,  G06F11/00 ,  H03K19/173 ,  H01L25/00

    CPC classification number: G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21 ,  H04N5/4401 ,  H04N5/46

    Abstract: A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

    Abstract translation: 公开了一种方法，其中提供了用于不同制造的大容量电子消费装置的便宜的集成电路，其中每个不同的制品必须执行不同的特殊功能。 在所有不同的构成中所需的共同功能在基本不可定制的部分中实现。 提供密集的可编程部分，用于实现特殊功能。 提供了接口电路，使得外部FPGA能够在系统开发过程中以系统运行速度执行特殊功能。 系统开发后，外部FPGA中实现的电路技术映射到掩模可编程部分。 形成单个掩模，使得集成电路的版本通过其定制的掩模可编程部分产生以执行特殊功能。 用于在系统开发过程中耦合到外部FPGA的I / O端子在正常操作期间可用，以提供系统板访问掩模可编程部分内的电路。

    Programmable application specific integrated circuit and logic cell therefor
    10.
    发明授权
    Programmable application specific integrated circuit and logic cell therefor 失效
    可编程专用集成电路和逻辑单元

    公开(公告)号：US5220213A

    公开(公告)日：1993-06-15

    申请号：US847137

    申请日：1992-03-06

    Applicant: Andrew K. Chan ,  Hua-Thye Chua

    Inventor： Andrew K. Chan ,  Hua-Thye Chua

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

    Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

    Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种功能强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

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