公开(公告)号：US07346876B2

公开(公告)日：2008-03-18

申请号：US10944323

申请日：2004-09-17

Applicant: Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

Inventor： Andrew K. Chan ,  Thomas M. Chan ,  Po Weng Chiu

IPC: G06F17/50 ,  G06F19/00 ,  G06F11/00 ,  H03K19/173 ,  H01L25/00

CPC classification number: G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21 ,  H04N5/4401 ,  H04N5/46

Abstract: A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

Abstract translation: 公开了一种方法，其中提供了用于不同制造的大容量电子消费装置的便宜的集成电路，其中每个不同的制品必须执行不同的特殊功能。 在所有不同的构成中所需的共同功能在基本不可定制的部分中实现。 提供密集的可编程部分，用于实现特殊功能。 提供了接口电路，使得外部FPGA能够在系统开发过程中以系统运行速度执行特殊功能。 系统开发后，外部FPGA中实现的电路技术映射到掩模可编程部分。 形成单个掩模，使得集成电路的版本通过其定制的掩模可编程部分产生以执行特殊功能。 用于在系统开发过程中耦合到外部FPGA的I / O端子在正常操作期间可用，以提供系统板访问掩模可编程部分内的电路。

公开(公告)号：US07782398B2

公开(公告)日：2010-08-24

申请号：US10235628

申请日：2002-09-04

Applicant: Thomas M. Chan ,  Harry J. Raftopoulos ,  Andrew K. Chan

Inventor： Thomas M. Chan ,  Harry J. Raftopoulos ,  Andrew K. Chan

IPC: H04N5/44 ,  H04N9/64

CPC classification number: G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21

Abstract: A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.

Abstract translation: 显示处理器集成电路（例如，用于电视机或数字照相机）包括显示处理器部分和片上可编程逻辑部分。 可以配置或编程片上可编程逻辑部分以实现定制的视频和/或图像增强功能。 因此，通过使可编程逻辑部分被适当地配置或编程，个人电视或照相机制造商可以将他/她自己的定制增强功能结合到显示处理器集成电路中。 在一个实施例中，可编程逻辑部分的编程涉及仅改变一个掩码，从而降低与实现定制视频/图像增强功能相关联的成本，复杂性和时间。

公开(公告)号：US06101074A

公开(公告)日：2000-08-08

申请号：US94462

申请日：1998-06-10

Applicant: James M. Apland ,  Andrew K. Chan

Inventor： James M. Apland ,  Andrew K. Chan

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K17/223 ,  H03K19/17772 ,  H03K19/17784

Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

Abstract translation: 保护电路在门阵列加电期间防止现场可编程门阵列中的逻辑模块中的电流尖峰。 保护电路在上电期间将电压提供给逻辑模块的内部禁止输入，直到由电荷泵输出的电压达到预定电压。 内部禁用输入端的电压关闭逻辑模块中的晶体管，并防止电流尖峰。 当电荷泵输出的电压达到预定电压时，保护电路不再将电压提供给逻辑模块的内部禁止输入。

公开(公告)号：US5726586A

公开(公告)日：1998-03-10

申请号：US744225

申请日：1996-11-05

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5416367A

公开(公告)日：1995-05-16

申请号：US189352

申请日：1994-01-31

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua T. Chua ,  William D. Cox

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17784 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的多个逻辑单元（“模块”）。 每个逻辑单元都是一个功能强大的通用逻辑构建块。 每个逻辑单元基本上由四个双输入与门，一个或两个六输入与门，三个多路复用器和D型触发器组成。

公开(公告)号：US5220213A

公开(公告)日：1993-06-15

申请号：US847137

申请日：1992-03-06

Applicant: Andrew K. Chan ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  Hua-Thye Chua

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17728 ,  H03K19/1737 ,  H03K19/17704

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种功能强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US07830449B2

公开(公告)日：2010-11-09

申请号：US11732434

申请日：2007-04-03

Applicant: Qinggang Zhou ,  Clyde H. Nagakura ,  Sheng-Fu Wu ,  Andrew K. Chan

Inventor： Qinggang Zhou ,  Clyde H. Nagakura ,  Sheng-Fu Wu ,  Andrew K. Chan

IPC: H04N7/01 ,  H04N11/02

CPC classification number: H04N7/0135 ,  G06T3/4023 ,  G09G5/363 ,  G09G2310/0229 ,  G09G2320/106 ,  G09G2340/0407 ,  H04N5/21 ,  H04N7/012

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract translation: 显示处理器集成电路包括显示处理器部分和片上可编程逻辑部分。 可编程逻辑部分可被配置为实现定制的视频和/或图像增强功能。 显示处理器部分执行基于块的运动检测。 如果对于给定的像素块没有检测到运动，则使用时间插值来填充块中的行间隙。 如果检测到运动，则使用空间插值填充行间隙。 为了保持精度而不会不适当地增加计算复杂度，在不检测到低角度倾斜条件的情况下采用较不复杂的高角度空间插值方法。 因此，在低角度倾斜条件下可以采用更计算密集的低角度空间插值方法。 在读取其他部分的同时进行插值处理的同时，通过采用流水线来编写段缓冲器的部分来减少集成电路成本。

公开(公告)号：US06426649B1

公开(公告)日：2002-07-30

申请号：US09751440

申请日：2000-12-29

Applicant: Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

Inventor： Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

IPC: H03K738

CPC classification number: H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778 ,  H03L7/183

Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

Abstract translation: 现场可编程门阵列包括可编程互连结构和多个逻辑单元。 每个逻辑单元包括与可编程互连结构具有直接互连的多个组合逻辑电路，以及用作寄存器的多个顺序逻辑元件，例如D型触发器。 组合逻辑电路可以直接连接到可编程互连结构，并且连接到顺序逻辑元件的输入端。 因此，逻辑单元包括与可编程互连结构的组合和注册连接。 此外，顺序元件之一可以选择性地从可编程互连结构接收专用输入。 逻辑单元的输出引线通过包括保护晶体管的驱动器连接到可编程互连结构。 保护晶体管的栅极耦合到与多个驱动器共享的主电荷泵以及与驱动器相关联的次级电荷泵。

公开(公告)号：US5898776A

公开(公告)日：1999-04-27

申请号：US754461

申请日：1996-11-21

Applicant: James M. Apland ,  David D. Eaton ,  Andrew K. Chan

Inventor： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

IPC: G01R31/317 ,  G01R31/3185 ,  H04L9/00

CPC classification number: G01R31/318519 ,  G01R31/31719 ,  G01R31/318555 ,  G01R31/31702 ,  G01R31/318558

Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

Abstract translation: 现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。 在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用， 。 还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。 因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。 提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

公开(公告)号：US5502315A

公开(公告)日：1996-03-26

申请号：US161504

申请日：1993-12-02

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L23/525 ,  H02L27/02

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。