Invention Grant
- Patent Title: Power-up circuit for field programmable gate arrays
- Patent Title (中): 现场可编程门阵列的上电电路
-
Application No.: US94462Application Date: 1998-06-10
-
Publication No.: US06101074APublication Date: 2000-08-08
- Inventor: James M. Apland , Andrew K. Chan
- Applicant: James M. Apland , Andrew K. Chan
- Applicant Address: CA Sunnyvale
- Assignee: QuickLogic Corporation
- Current Assignee: QuickLogic Corporation
- Current Assignee Address: CA Sunnyvale
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H03K17/22 ; H03K19/177
Abstract:
A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.
Public/Granted literature
- USD425408S Bottle Public/Granted day:2000-05-23
Information query