公开(公告)号：US08091001B2

公开(公告)日：2012-01-03

申请号：US11565441

申请日：2006-11-30

Applicant: Stephen U. Yao ,  Darwin D. Q. Samson ,  Ket-Chong Yap

Inventor： Stephen U. Yao ,  Darwin D. Q. Samson ,  Ket-Chong Yap

IPC: G01R31/28

CPC classification number: G01R31/318516

Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.

Abstract translation: 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑，从而提供组合逻辑的测试。 本发明的一些实施例提供了一种用于在可编程逻辑设备中测试应用特定标准产品（ASSP）的功能逻辑块的方法，所述方法包括：将输入值存储到寄存器中; 将输入值从寄存器传递给组合逻辑; 从组合逻辑产生输出值; 将组合逻辑的输出值传递给寄存器; 将输出值保存在寄存器中; 并从寄存器读取输出值。

公开(公告)号：US08018248B2

公开(公告)日：2011-09-13

申请号：US11525275

申请日：2006-09-21

Applicant: Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

Inventor： Ket-Chong Yap ,  Senani Gunaratna ,  Wilma Waiman Shiao

IPC: H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.

Abstract translation: 集成电路包括可编程逻辑器件，专用器件和两者之间的接口电路。 可以容易地修改接口电路以适应可嵌入到集成电路中的各种专用设备的不同接口I / O需求。 在一个实施例中，接口电路可以使用多个掩码可编程单向接口缓冲电路来实现。 可以通过在集成电路的单个金属层中的接口缓冲电路中重新布线导体，基于期望的专用器件的需要来反转任何所需数量的接口缓冲电路的方向。 在另一个实施例中，接口电路可以使用硬件可配置的双向接口缓冲电路来实现。

公开(公告)号：US07443222B1

公开(公告)日：2008-10-28

申请号：US11753531

申请日：2007-05-24

Applicant: Timothy Saxe ,  Senani Gunaratna ,  Stephen U. Yao

Inventor： Timothy Saxe ,  Senani Gunaratna ,  Stephen U. Yao

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: An implementation of an apparatus and method to generate a dynamically controlled clock is provided. The resulting clock reduces otherwise produced narrow clock pulses and allows for control from two separate control signals. A first control signal indicates a low power mode, for example a chip-wide low power mode. A second control signal indicates a user-selected mode to shutdown a selected clock.

Abstract translation: 提供了一种用于生成动态控制时钟的装置和方法的实现。 所产生的时钟减少了另外产生的窄时钟脉冲，并允许从两个单独的控制信号进行控制。 第一控制信号表示低功率模式，例如芯片级的低功率模式。 第二控制信号指示用户选择的关闭所选时钟的模式。

公开(公告)号：US07187228B1

公开(公告)日：2007-03-06

申请号：US09887834

申请日：2001-06-22

Applicant: Rajiv Jain ,  Richard J. Wong

Inventor： Rajiv Jain ,  Richard J. Wong

IPC: H01H37/76

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired. Programming an antifuse in accordance with the present invention results in an antifuse structure with a conductive filament that is in good contact with both conductive elements, which reduces resistance in the antifuse and increases yield. A programming circuitry is provided that includes a current source and a voltage clamp to program antifuses according the described method.

Abstract translation: 设置在两个导电元件之间的可编程材料的反熔丝使用相反极性的多个电流脉冲进行编程。 第一脉冲具有不足以完全编程反熔丝的电流，即产生期望的电阻水平。 在一个实施例中，第一脉冲是电流限制的。 第一脉冲有利地通过反熔丝材料从一个导电元件驱动导电细丝，反熔丝材料可以是例如非晶硅。 然而，来自第一脉冲的导电细丝具有有限的横截面积。 使用具有相反极性的相同电压和具有增加幅度的电流的编程脉冲将材料从另一导电元件驱动到反熔丝材料中，这增加了导电细丝的横截面积，从而降低了电阻。 如果需要，可以使用额外的编程脉冲以及电流限制脉冲。 根据本发明编写反熔丝导致具有与两个导电元件良好接触的导电细丝的反熔丝结构，这降低了反熔丝中的电阻并提高了产量。 提供了一种编程电路，其包括电流源和用于根据所描述的方法编程反熔丝的电压钳。

公开(公告)号：US6097651A

公开(公告)日：2000-08-01

申请号：US345971

申请日：1999-06-30

Applicant: Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

Inventor： Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/00

CPC classification number: G11C11/417 ,  G11C7/1045 ,  G11C7/12

Abstract: A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

Abstract translation: 随机存取存储器（RAM）装置包括存储器单元中的缓冲器，以将锁存电路与读位线隔离。 因此，避免了由读取位线上的电容性负载引起的读取干扰错误。 此外，对于写位线的预充电要求被简化，因为缓冲器允许存储单元中的锁存电路的优化。 RAM装置包括在执行写入操作之前将写入位线预充电到接地参考电压的预充电电路。 通过将写位线预充电到接地参考电压，避免了由写位线上的电容负载引起的写干扰问题。 此外，通过将写入位线耦合到接地参考电压，通过对写入位线进行预充电，很少或没有电力消耗。

公开(公告)号：US6084428A

公开(公告)日：2000-07-04

申请号：US931897

申请日：1997-09-17

Applicant: Paige A. Kolze ,  James A. Apland

Inventor： Paige A. Kolze ,  James A. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A field programmable gate array has columns of logic modules. A programming conductor used to conduct programming current to program antifuses of the field programmable gate array extends between two adjacent columns of logic modules. First wire segments extend from the programming conductor and toward the logic modules of a first of the two adjacent columns. Second wire segments extend the opposite direction from the programming conductor and toward logic modules of the second of the two adjacent columns. Programming current used to program antifuses disposed along the first wire segments as well as antifuses disposed along the second wire segments can be supplied from the same programming conductor that extends between the two columns of logic modules. The logic modules of the first column are mirrored versions of the logic modules of the second column.

Abstract translation: 现场可编程门阵列具有逻辑模块列。 用于编程电流编程现场可编程门阵列的反熔丝的编程导体在两个相邻列的逻辑模块之间延伸。 第一线段从编程导体延伸到两个相邻列中的第一个的逻辑模块。 第二线段从编程导体向相反方向延伸，并且朝两个相邻列中的第二列的逻辑模块延伸。 用于编程沿着第一线段设置的反熔丝的编程电流以及沿着第二线段设置的反熔丝可以从在两列逻辑模块之间延伸的相同编程导体提供。 第一列的逻辑模块是第二列逻辑模块的镜像版本。

公开(公告)号：US5986468A

公开(公告)日：1999-11-16

申请号：US988432

申请日：1997-12-11

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

公开(公告)号：US5900742A

公开(公告)日：1999-05-04

申请号：US667783

申请日：1996-06-21

Applicant: Paige A. Kolze ,  William D. Cox ,  Kevin K. Yee

Inventor： Paige A. Kolze ,  William D. Cox ,  Kevin K. Yee

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/1778

Abstract: An interface cell for a programmable integrated circuit includes a pad, an input buffer, a first routing conductor, a plurality of second routing conductors, and a plurality of antifuses. The input of the input buffer is coupled to the pad and the output of the input buffer is coupled to the first routing conductor so that an input signal from the pad can be supplied onto the first routing conductor without passing through any programmed antifuses. The second routing conductors extend parallel to one another in a direction perpendicular to the direction in which the first routing conductor extends. The second routing conductors cross the first routing conductor and then pass out of the interface cell and into a routing channel of the programmable integrated circuit. One of the antifuses is disposed at each location where one of the second routing conductors crosses the first routing conductor. Accordingly, an input signal from the pad can be supplied onto any desired one of the second routing conductors of the routing channel by programming only one antifuse. The interface cell contains an enablable register, the control inputs of which can be independently driven from any conductor in the adjacent routing channel. Combinatorial and registered outputs of the interface cell can be simultaneously routed to the routing channel and some interface cell outputs have 2.times. drive strength.

Abstract translation: 用于可编程集成电路的接口单元包括衬垫，输入缓冲器，第一布线导体，多个第二布线导体以及多个反熔丝。 输入缓冲器的输入耦合到焊盘，并且输入缓冲器的输出耦合到第一布线导体，使得来自焊盘的输入信号可以被提供到第一布线导体上，而不通过任何编程的反熔丝。 第二布线导体在垂直于第一布线导体延伸的方向的方向上彼此平行延伸。 第二路由导体穿过第一路由导体，然后从接口单元传出并进入可编程集成电路的路由信道。 一个反熔丝设置在每个位置，其中一个第二布线导体与第一布线导体交叉。 因此，通过仅编程一个反熔丝，可以将来自焊盘的输入信号提供给路由通道的任何所需的第二路由导体。 接口单元包含一个可用的寄存器，其控制输入可以独立地从相邻路由通道中的任何导体驱动。 接口单元的组合和注册输出可以同时路由到路由通道，一些接口单元输出具有2x驱动强度。

公开(公告)号：US5880512A

公开(公告)日：1999-03-09

申请号：US768601

申请日：1996-12-18

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

公开(公告)号：US5786268A

公开(公告)日：1998-07-28

申请号：US904387

申请日：1997-08-01

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00 ,  H01L21/44

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract translation: 公开了具有抗熔丝的防潮和门阵列，其具有高的热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改善的制造产量和更可控的电特性。 一些反熔丝包括反熔丝通孔中的间隔物。 在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。 在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。