FPGA programming structure for ATPG test coverage
    1.
    发明授权
    FPGA programming structure for ATPG test coverage 有权
    FPGA编程结构,用于ATPG测试覆盖

    公开(公告)号:US08091001B2

    公开(公告)日:2012-01-03

    申请号:US11565441

    申请日:2006-11-30

    IPC分类号: G01R31/28

    CPC分类号: G01R31/318516

    摘要: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.

    摘要翻译: 通过可编程逻辑中的编程电路将输入和/或输出测试值路由输入和/或输出测试值作为信号从专用逻辑返回到专用逻辑,从而提供组合逻辑的测试。 本发明的一些实施例提供了一种用于在可编程逻辑设备中测试应用特定标准产品(ASSP)的功能逻辑块的方法,所述方法包括:将输入值存储到寄存器中; 将输入值从寄存器传递给组合逻辑; 从组合逻辑产生输出值; 将组合逻辑的输出值传递给寄存器; 将输出值保存在寄存器中; 并从寄存器读取输出值。