Invention Grant
- Patent Title: FPGA programming structure for ATPG test coverage
- Patent Title (中): FPGA编程结构,用于ATPG测试覆盖
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Application No.: US11565441Application Date: 2006-11-30
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Publication No.: US08091001B2Publication Date: 2012-01-03
- Inventor: Stephen U. Yao , Darwin D. Q. Samson , Ket-Chong Yap
- Applicant: Stephen U. Yao , Darwin D. Q. Samson , Ket-Chong Yap
- Applicant Address: US CA Sunnyvale
- Assignee: QuickLogic Corporation
- Current Assignee: QuickLogic Corporation
- Current Assignee Address: US CA Sunnyvale
- Agency: Silicon Valley Patent Group LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.
Public/Granted literature
- US20080133988A1 FPGA Programming Structure for ATPG Test Coverage Public/Granted day:2008-06-05
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