公开(公告)号：US06101074A

公开(公告)日：2000-08-08

申请号：US94462

申请日：1998-06-10

Applicant: James M. Apland ,  Andrew K. Chan

Inventor： James M. Apland ,  Andrew K. Chan

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K17/223 ,  H03K19/17772 ,  H03K19/17784

Abstract: A protection circuit prevents a current spike in a logic module in a field programmable gate array during power up of the gate array. The protection circuit supplies a voltage onto an internal disable input of the logic module during power up until a voltage output by a charge pump reaches a predetermined voltage. The voltage on the internal disable input turns off transistor(s) in the logic module and prevents the current spike. When the voltage output by the charge pump reaches the predetermined voltage, the protection circuit no longer supplies the voltage to the logic module's internal disable input.

Abstract translation: 保护电路在门阵列加电期间防止现场可编程门阵列中的逻辑模块中的电流尖峰。 保护电路在上电期间将电压提供给逻辑模块的内部禁止输入，直到由电荷泵输出的电压达到预定电压。 内部禁用输入端的电压关闭逻辑模块中的晶体管，并防止电流尖峰。 当电荷泵输出的电压达到预定电压时，保护电路不再将电压提供给逻辑模块的内部禁止输入。

公开(公告)号：US5955892A

公开(公告)日：1999-09-21

申请号：US931898

申请日：1997-09-17

Applicant: James M. Apland

Inventor： James M. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: In a programmable integrated circuit such as a field programmable gate array (see FIG. 6), a programming driver is coupled to one end of a programming conductor and a test transistor/test antifuse structure is coupled to the other end of the programming driver. To test the continuity of the programming conductor, the test transistor is controlled to be conductive. If the programming driver can drive an adequately large amount of programming current through the length of the programming conductor to the conductive test transistor and the test antifuse such that the test antifuse programs, then it is determined that the programming conductor has adequate continuity. In some embodiments a second test transistor that should be permanently nonconductive is disposed in parallel with the test antifuse.

Abstract translation: 在诸如现场可编程门阵列（见图6）的可编程集成电路中，编程驱动器耦合到编程导体的一端，并且测试晶体管/测试反熔丝结构耦合到编程驱动器的另一端。 为了测试编程导体的连续性，测试晶体管被控制为导电的。 如果编程驱动器可以通过编程导体的长度驱动足够大的编程电流到导电测试晶体管和测试反熔丝，使得测试反熔丝程序，则确定编程导体具有足够的连续性。 在一些实施例中，应该永久不导电的第二测试晶体管与测试反熔丝平行设置。

公开(公告)号：US5132936A

公开(公告)日：1992-07-21

申请号：US675021

申请日：1991-03-25

Applicant: Paul D. Keswick ,  James M. Apland

Inventor： Paul D. Keswick ,  James M. Apland

IPC: G11C7/12 ,  G11C11/4094

CPC classification number: G11C7/12 ,  G11C11/4094

Abstract: An improved MOS memory circuit using an MOS clamp circuit on the bitlines which turns on when the voltage on a bitline exceeds a predetermined voltage, thereby drawing current from the bitline to remove excess charge and return the bitline to the predetermined voltage. The clamp circuit of this invention allows prompt read access because reading is not substantially delayed by the excess bitline charge.

Abstract translation: 在位线上的电压超过预定电压时，在位线上使用MOS钳位电路的改进的MOS存储器电路，其被导通，从而从位线引出电流以去除过量电荷并将位线返回到预定电压。 本发明的钳位电路允许迅速的读取访问，因为读数基本上不被多余的位线电荷延迟。

公开(公告)号：US6097651A

公开(公告)日：2000-08-01

申请号：US345971

申请日：1999-06-30

Applicant: Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

Inventor： Andrew K. Chan ,  James M. Apland ,  Ket-Chong Yap

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/417 ,  G11C7/00

CPC classification number: G11C11/417 ,  G11C7/1045 ,  G11C7/12

Abstract: A random access memory (RAM) device includes a buffer in the memory cell to isolate the latching circuit from the read bit line. Consequently, read disturb errors caused by capacitive loading on the read bit line are avoided. Further, the precharge requirements on the write bit line are simplified because the buffer permits optimization of the latching circuit in the memory cell. The RAM device includes a precharge circuit that precharges the write bit line to a ground reference voltage prior to performing write operations. By precharging the write bit line to ground reference voltage, write disturb problems caused by capacitive loading on the write bit line are avoided. Further, by coupling the write bit line to ground reference voltage, little or no power is consumed by precharging the write bit line.

Abstract translation: 随机存取存储器（RAM）装置包括存储器单元中的缓冲器，以将锁存电路与读位线隔离。 因此，避免了由读取位线上的电容性负载引起的读取干扰错误。 此外，对于写位线的预充电要求被简化，因为缓冲器允许存储单元中的锁存电路的优化。 RAM装置包括在执行写入操作之前将写入位线预充电到接地参考电压的预充电电路。 通过将写位线预充电到接地参考电压，避免了由写位线上的电容负载引起的写干扰问题。 此外，通过将写入位线耦合到接地参考电压，通过对写入位线进行预充电，很少或没有电力消耗。

公开(公告)号：US5966028A

公开(公告)日：1999-10-12

申请号：US929654

申请日：1997-09-17

Applicant: James M. Apland

Inventor： James M. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programmable integrated circuit (see FIG. 5) has a plurality of linearly extending wire segments with antifuses disposed between each wire segment and a plurality of linearly extending programming conductors that are perpendicular to the wire segments. A plurality of programming transistors are disposed between a corresponding respective one of the wire segments and a corresponding respective one of the programming conductors. A programming control conductor extending from a programming control driver is coupled to the gate electrode of each of the programming transistors as well as the gate electrode of a test transistor. A test antifuse is coupled in series with the test transistor. When the programming control conductor can drive the test transistor with an adequately high voltage to program the test antifuse, it is assumed that the programming control conductor can drive the programming transistor with an adequately high voltage to program the antifuses. The test transistor may be disposed on the programming control conductor at the opposite end from the programming control driver.

Abstract translation: 可编程集成电路（参见图5）具有多个线性延伸的线段，其中反熔丝设置在每个线段和垂直于线段的多个线性延伸的编程导体之间。 多个编程晶体管被布置在相应的一个线段和对应的相应的一个编程导体之间。 从编程控制驱动器延伸的编程控制导体耦合到每个编程晶体管的栅电极以及测试晶体管的栅电极。 测试反熔丝与测试晶体管串联耦合。 当编程控制导体可以用足够高的电压驱动测试晶体管来对测试反熔丝进行编程时，假设编程控制导体可以用足够高的电压来驱动编程晶体管来编程反熔丝。 测试晶体管可以设置在与编程控制驱动器相对的编程控制导体上。

公开(公告)号：US5898776A

公开(公告)日：1999-04-27

申请号：US754461

申请日：1996-11-21

Applicant: James M. Apland ,  David D. Eaton ,  Andrew K. Chan

Inventor： James M. Apland ,  David D. Eaton ,  Andrew K. Chan

IPC: G01R31/317 ,  G01R31/3185 ,  H04L9/00

CPC classification number: G01R31/318519 ,  G01R31/31719 ,  G01R31/318555 ,  G01R31/31702 ,  G01R31/318558

Abstract: A field programmable gate array has a security antifuse which when programmed prevents readout of data indicative of how the interconnect structure is programmed but which does not prevent readout of data indicative of which other antifuses are programmed. In some embodiments, the programming control shift registers adjacent the left and right sides are the field programmable gate array are disabled when the security antifuse is programmed but the programming control shift registers adjacent the top and bottom sides of the field programmable gate array are not disabled. A second security antifuse is also provided which when programmed disables a JTAG boundary scan register but does not disable a JTAG bypass register. Information can therefore be shifted through the JTAG test circuitry without allowing the JTAG circuitry to be used to extract information indicative of how the interconnect structure is programmed. Logic module and interface cell scan paths are provided and special test instructions are supported which allow test vectors to be loaded into the logic module and interface cell scan paths.

Abstract translation: 现场可编程门阵列具有安全反熔丝，其在编程时防止读出指示互连结构如何编程的数据，但是不防止读出指示哪个其它反熔丝被编程的数据。 在一些实施例中，当安全反熔丝被编程但是与现场可编程门阵列的顶侧和底侧相邻的编程控制移位寄存器未被禁用时，与左侧和右侧相邻的编程控制移位寄存器被禁用， 。 还提供了第二个安全反熔丝，当编程时禁用JTAG边界扫描寄存器，但不禁用JTAG旁路寄存器。 因此，信息可以通过JTAG测试电路转移，而不允许JTAG电路提取指示互连结构如何编程的信息。 提供逻辑模块和接口单元扫描路径，并支持特殊测试指令，允许将测试向量加载到逻辑模块和接口单元扫描路径中。

公开(公告)号：US6140837A

公开(公告)日：2000-10-31

申请号：US161192

申请日：1998-09-25

Applicant: David D. Eaton ,  Richard J. Wong ,  James M. Apland

Inventor： David D. Eaton ,  Richard J. Wong ,  James M. Apland

IPC: H01L21/8234 ,  H01L27/118 ,  H03K19/173 ,  G05F1/10 ,  H03K19/175

CPC classification number: H01L21/823462 ,  H01L27/11807

Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers. In some embodiments, the second power input terminal receives a voltage higher than the first supply voltage during antifuse programming such that the oscillating signal that drives the charge pumps has a larger amplitude thereby allowing back bias threshold voltages of transistors in the charge pumps to be overcome, facilitating starting of the charge pumps, and/or increasing charge pump efficiency.

Abstract translation: 可编程器件具有采用反熔丝的数字逻辑元件和可编程互连结构，反熔丝是可编程的，以将选定的数字逻辑元件连接在一起。 在正常电路操作期间，使用第一电力输入端子以在第一电力输入端子上接收的第一电源电压为数字逻辑元件供电。 在正常电路操作期间，使用第二电力输入端子来保护可编程器件的电路免受可编程器件外部的电路驱动到可编程器件的端子的高电压信号。 在反熔丝编程期间，第二电源输入端用于驱动编程驱动器和/或编程控制驱动器的电荷泵。 在一些实施例中，第二电力输入端子在反熔丝编程期间接收高于第一电源电压的电压，使得驱动电荷泵的振荡信号具有较大的幅度，从而允许克服电荷泵中晶体管的反向偏置阈值电压 ，促进电荷泵的启动和/或增加电荷泵效率。

公开(公告)号：US6081129A

公开(公告)日：2000-06-27

申请号：US931893

申请日：1997-09-17

Applicant: James M. Apland ,  Paige A. Kolze

Inventor： James M. Apland ,  Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H01L25/00

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG. 15), the gate of no programming transistor coupled to an output routing wire segment of the logic module (such as transistor 216) is permanently connected to the gate of any programming transistor coupled to an input routing wire segment of the logic module (such as transistors 200, 201 and 202).

Abstract translation: 公开了一种采用反熔丝的现场可编程门阵列（FPGA）的编程架构。 为了测试编程导体，编程晶体管，布线线段和未编程FPGA（参见图16）的逻辑模块的组合部分的完整性，数字逻辑值的组合被提供到组合部分的输入端 测试模式。 如果正确的数字值不由组合部分输出，则确定存在缺陷。 由组合部分输出的数字值被捕获在逻辑模块的触发器中，并以扫描输出测试模式从FPGA中移出。 还公开了编程晶体管，编程导体和布线线段结构，其有助于这种测试。 在一个实施例中（参见图15），耦合到逻辑模块（例如晶体管216）的输出布线线段的无编程晶体管的栅极永久连接到耦合到输入布线线段的任何编程晶体管的栅极 的逻辑模块（例如晶体管200,201和202）。

公开(公告)号：US06542096B2

公开(公告)日：2003-04-01

申请号：US09939533

申请日：2001-08-24

Applicant: Andrew K. Chan ,  James M. Apland ,  Senani Gunaratna ,  SunilKumar G. Mudunuri ,  Ket-Chong Yap

Inventor： Andrew K. Chan ,  James M. Apland ,  Senani Gunaratna ,  SunilKumar G. Mudunuri ,  Ket-Chong Yap

IPC: H03M900

CPC classification number: G11C7/222 ,  G11C7/1006 ,  G11C7/22 ,  H04J3/0685 ,  H04L7/0008 ,  H04L7/0083 ,  H04L7/033 ,  H04L7/10

Abstract: In accordance with the invention, a serializer/deserializer core of a field programmable gate array includes a channel clock and a data channel. The data channel can serialize and deserialize data in two modes. In the first mode, an embedded clock signal is recovered from the data. In the second mode, a clock signal is provided by the channel clock. A selection signal determines in which mode each of the data channels in the serializer/deserializer core operates. An stair-step clock generator generates a series of rising edge signals used to serialize and deserialize data. The number of bits serialized and deserialized is determined by the control signals to a set of multiplexers in the stair-step clock generator which determine how many registers in the stair-step clock generator are activated.

Abstract translation: 根据本发明，现场可编程门阵列的串行器/解串器核心包括通道时钟和数据通道。 数据通道可以在两种模式下对数据进行序列化和反序列化。 在第一模式中，从数据中恢复嵌入的时钟信号。 在第二模式中，时钟信号由通道时钟提供。 选择信号确定串行器/解串器核心中的每个数据信道在哪种模式下操作。 阶梯式时钟发生器产生一系列用于串行化和反序列化数据的上升沿信号。 串行化和反序列化的位数由控制信号确定到楼梯级时钟发生器中的一组多路复用器，确定楼梯级时钟发生器中有多少个寄存器被激活。

公开(公告)号：US5986469A

公开(公告)日：1999-11-16

申请号：US932890

申请日：1997-09-17

Applicant: David D. Eaton ,  Paige A. Kolze ,  James M. Apland

Inventor： David D. Eaton ,  Paige A. Kolze ,  James M. Apland

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177

CPC classification number: H03K19/17764 ,  H03K17/223 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A programmable integrated circuit (see FIG. 9) has a plurality of L-shaped programming power buses (for example, 126, 130, 129 and 127) that extend along sides of the integrated circuit. Each L-shaped programming power bus extends along two adjacent sides of the integrated circuit such that legs of two L-shaped programming power buses extend along each of the sides. There are four pluralities of programming drivers (for example, 110, 117, 115 and 112), one plurality being associated with each of the four sides. There are also four programming current multiplexers (for example, 118, 125, 123 and 120), one associated with each of the sides. A programming driver of one of the plurality of programming drivers is selectively couplable to one of the two L-shaped programming power bus legs that extends along the associated side of the integrated circuit via the programming current multiplexer associated with that side. Additional pluralities of programming drivers and additional programming current multiplexers can be provided.

Abstract translation: 可编程集成电路（见图9）具有沿着集成电路的侧面延伸的多个L形编程电源总线（例如，126,130,129和127）。 每个L形编程电源总线沿着集成电路的两个相邻侧延伸，使得两个L形编程电源总线的脚沿着每个侧面延伸。 有四种编程驱动程序（例如，110,117,115和112），一个与四个方面中的每一个相关联。 还有四个编程电流多路复用器（例如，118,125,123和120），一个与每个侧面相关联。 多个编程驱动器之一的编程驱动器可选择性地耦合到两个L形编程功率总线支路中的一个，其经由与该侧相关联的编程电流复用器沿着集成电路的相关侧延伸。 可以提供额外的多个编程驱动器和附加的编程电流多路复用器。