公开(公告)号：US06812872B1

公开(公告)日：2004-11-02

申请号：US10346704

申请日：2003-01-17

Applicant: Jinghui Lu

Inventor： Jinghui Lu

IPC: H03M900

CPC classification number: H03M9/00 ,  H03L7/06

Abstract: Described are high-speed parallel-to-serial converters. The converters include data combiners with differential current-steering circuits that respond to parallel data bits by producing complementary current signals representing a differential, serialized version of the parallel data bits. One embodiment includes inductive and resistive loads to equalize the gain over the frequency of interest to reduce data-deterministic jitter.

Abstract translation: 描述了高速并行到串行转换器。 转换器包括具有差分电流 - 转向电路的数据组合器，其通过产生表示并行数据位的差分串行版本的互补电流信号来响应并行数据位。 一个实施例包括电感和电阻负载以均衡感兴趣频率上的增益以减少数据确定性抖动。

公开(公告)号：US06791483B2

公开(公告)日：2004-09-14

申请号：US10601572

申请日：2003-06-24

Applicant: Shinji Hattori

Inventor： Shinji Hattori

IPC: H03M900

CPC classification number: H03M9/00

Abstract: A parallel/serial conversion circuit is provided, which comprises a parallel/serial conversion section for converting first parallel data to first serial data and converting second parallel data to second serial data, and a shift clock signal generation section for generating a shift clock signal. The parallel/serial conversion section converts the first parallel data to the first serial data by shifting the first parallel data in response to the shift clock signal. The parallel/serial conversion section converts the second parallel data to the second serial data by shifting the second parallel data in response to the shift clock signal. A combination of the first serial data and the second serial data indicates bit separation, a logic value ‘0’, or a logic value ‘1’. The shift clock signal generation section generates the shift clock signal by combining the first serial data and the second serial data.

Abstract translation: 提供一种并行/串行转换电路，它包括并行/串行转换部分，用于将第一并行数据转换成第一串行数据并将第二并行数据转换成第二串行数据;以及移位时钟信号产生部分，用于产生移位时钟信号。 并行/串行转换部分通过响应于移位时钟信号移位第一并行数据来将第一并行数据转换为第一串行数据。 并行/串行转换部分通过响应于移位时钟信号移位第二并行数据来将第二并行数据转换成第二串行数据。 第一串行数据和第二串行数据的组合指示位分离，逻辑值“0”或逻辑值“1”。 移位时钟信号生成部通过组合第一串行数据和第二串行数据来生成移位时钟信号。

公开(公告)号：US06710726B2

公开(公告)日：2004-03-23

申请号：US10317327

申请日：2002-12-12

Applicant: Ji-Young Kim ,  Jae-yup Lee

Inventor： Ji-Young Kim ,  Jae-yup Lee

IPC: H03M900

CPC classification number: H03M9/00

Abstract: A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal. Instead of using the first clock signal input with the data signal, the serializer-deserializer circuit uses a signal, which is generated by an oscillator and thus has a small amount of jitter, as an input clock to the PLL so that a reference clock signal without noise is generated to improve the operation of the serializer-deserializer circuit. In addition, the reference clock signal output from the PLL is locked to the data signal to increase margins for setup and hold time during the latch operation of the data signal.

Abstract translation: 提供了一种具有增加的建立和保持时间余量的串行器 - 解串器电路。 串行器 - 解串器电路包括数据偏移控制电路，锁存电路，串行转换器电路和锁相环（PLL）。 数据偏移控制电路接收第一时钟信号和数据信号，延迟数据信号，并响应于参考时钟信号输出延迟的数据信号。 锁存电路根据参考时钟信号锁存和输出延迟的数据信号。 串行转换器电路响应于参考时钟信号接收和串行锁存电路的输出信号以输出串行数据。 PLL根据外部参考时钟信号产生参考时钟信号。 串行器 - 解串器电路不是使用与数据信号一起输入的第一时钟信号，而是使用由振荡器产生的信号，因此具有少量的抖动作为PLL的输入时钟，使得参考时钟信号 不产生噪声，从而改善了串串器 - 解串器电路的运行。 此外，从PLL输出的参考时钟信号被锁定到数据信号，以在数据信号的锁存操作期间增加用于建立和保持时间的裕度。

公开(公告)号：US06686856B1

公开(公告)日：2004-02-03

申请号：US10300255

申请日：2002-11-20

Applicant: Charles Wang ,  Miaobin Gao ,  Gladney Asada

Inventor： Charles Wang ,  Miaobin Gao ,  Gladney Asada

IPC: H03M900

CPC classification number: H03M9/00

Abstract: Systems and methods of converting data streams from one clocking domain to another are described. In one aspect, a clocking domain conversion system includes an input, an output, a routing circuit, and a clock generator. The input is operable to simultaneously load N input bits during each load cycle at an average rate RIN, wherein N has an integer value of at least 1. The output is operable to simultaneously output M output bits during each output cycle at an average rate ROUT, wherein M has an integer value of at least 1 and M≠N. The routing circuit is operable to route the N input bits from the input to the output at a clocking rate RCLK and with a dividing ratio K of the routing circuit data rate relative to the higher of the input and output data rates, given by if K = N · R CLK M · R OUT R IN R OUT . The clock generator is operable to generate a clock signal for controlling the routing circuit and characterized by a non-uniform sequence of pulses having an average period T between successive pulses, given by T = K R CLK .

Abstract translation: 描述将数据流从一个时钟域转换到另一个时钟域的系统和方法。 一方面，时钟域转换系统包括输入，输出，路由电路和时钟发生器。 该输入可操作以在每个负载周期期间以平均速率RIN同时加载N个输入位，其中N具有至少为1的整数值。该输出可操作以在平均速率ROUT的每个输出周期期间同时输出M个输出位 其中M具有至少为1且M

公开(公告)号：US06583737B2

公开(公告)日：2003-06-24

申请号：US10090324

申请日：2002-03-04

Applicant: Karl Schrödinger

Inventor： Karl Schrödinger

IPC: H03M900

CPC classification number: H04L25/14 ,  H04J14/02 ,  H04J14/08

Abstract: The device and method compensate for propagation differences between n serial data streams each transmitted over parallel optical lines. Data that can be transmitted via the n serial data streams are configured as m-bit words. The device has n regeneration devices in which data of the data stream can be regenerated. A data output and a clock pulse output of the regeneration devices are connected to a propagation time control device so that the regenerated data and the regenerated clock pulse can be transmitted to a data input or to a clock pulse input of the propagation time control devices. The propagation time control devices each have a demultiplexer for dividing the regenerated data as well as the regenerated clock pulses with a ratio of 1:(x·m), and each have an alignment device for distributing the divided regenerated data on x·m parallel data outputs of the propagation time control devices.

公开(公告)号：US06567020B2

公开(公告)日：2003-05-20

申请号：US09941320

申请日：2001-08-28

Applicant: Antti Aunio

Inventor： Antti Aunio

IPC: H03M900

CPC classification number: H04B14/046

Abstract: The invention relates to a method and an arrangement for reducing interference created in an output signal in connection with signal conversion. The arrangement may employ two structural sets, whereof the arrangement comprises at least one. The first structural set comprises a modulator (10) arranged to modulate the signal, and a DA converter (30) arranged to convert the serial-mode input signal arriving from the modulator into an analogue output signal. In addition, the first structural set comprises a serial/parallel converter (20) arranged to convert the modulated signal into parallel mode, and a divider (40) for generating a clock signal, the frequency of the clock signal generated by the divider being lower than the frequency of the clock signal used in serial-mode input signal transmission. The divider (40) is arranged to simultaneously clock several signals to the DA converter (30). The second structural set comprises an AD converter (70) arranged to convert an analogue input signal into several parallel digital output signals. In addition, the second structural set comprises a parallel/serial converter (80) arranged to receive several simultaneously arriving digital signals for conversion into serial-mode signals using a clock signal, the frequency of which being lower than the frequency of the clock signal used in serial-mode signal transmission.

公开(公告)号：US06556152B2

公开(公告)日：2003-04-29

申请号：US09909499

申请日：2001-07-20

Applicant: Walter Michael Pitio ,  Donald David Shugard

Inventor： Walter Michael Pitio ,  Donald David Shugard

IPC: H03M900

CPC classification number: H03M9/00

Abstract: A deserializer is disclosed that incorporates a detection and feedback mechanism for ensuring that the deserializer samples a serialized stream of bits at advantageous times. Furthermore, a deserializer is disclosed that can operate at a frequency that is below the bit rate of the serialized stream of bits. The illustrative embodiment comprises: a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on the first binary waveform and on the first clock signal; a second bi-stable storage device for receiving the first binary waveform and a second clock signal and for generating a third binary waveform based on the first binary waveform and on the second clock signal; and unanimity logic for generating a fourth binary waveform based on a coincidence function of the second binary waveform and the third binary waveform.

Abstract translation: 公开了一种解串器，其包括检测和反馈机制，用于确保解串器在有利时间对串行化的比特流进行采样。 此外，公开了可以以低于串行化比特流的比特率的频率操作的解串器。 说明性实施例包括：第一双稳态存储装置，用于接收第一二进制波形和第一时钟信号，并用于基于第一二进制波形和第一时钟信号产生第二二进制波形; 第二双稳态存储装置，用于接收第一二进制波形和第二时钟信号，并用于基于第一二进制波形和第二时钟信号产生第三二进制波形; 以及用于基于第二二进制波形和第三二进制波形的一致函数产生第四二进制波形的一致逻辑。

公开(公告)号：US06509851B1

公开(公告)日：2003-01-21

申请号：US09538201

申请日：2000-03-30

Applicant: Leah S. Clark ,  Steven P. Larky

Inventor： Leah S. Clark ,  Steven P. Larky

IPC: H03M900

CPC classification number: H03M9/00

Abstract: An apparatus comprising an array of storage elements, a first circuit, and a second circuit. The array of storage elements may be configured to (i) store a first bit of data in response to a write address and a first edge of a first clock signal, (ii) store a second bit of data in response to the write address and a second edge of the first clock signal, and (iii) present one or more of the first and second bits in response to a read address. The first and second edges of the first clock generally have opposite polarities. The first circuit may be configured to generate the first clock signal in response to a serial data stream and a strobe signal. The second circuit may be configured to generate the write address and the read address in response to the first clock signal and a second clock signal.

Abstract translation: 一种包括存储元件阵列，第一电路和第二电路的装置。 存储元件阵列可以被配置为（i）响应于第一时钟信号的写入地址和第一个边沿来存储第一位数据，（ii）响应于写入地址存储第二位数据;以及 第一时钟信号的第二边缘，以及（iii）响应于读取地址呈现第一和第二位中的一个或多个。 第一时钟的第一和第二边通常具有相反的极性。 第一电路可以被配置为响应于串行数据流和选通信号而产生第一时钟信号。 第二电路可以被配置为响应于第一时钟信号和第二时钟信号而产生写入地址和读取地址。

公开(公告)号：US06459393B1

公开(公告)日：2002-10-01

申请号：US09074844

申请日：1998-05-08

Applicant: John Emery Nordman

Inventor： John Emery Nordman

IPC: H03M900

CPC classification number: H04L25/45 ,  H03M9/00

Abstract: An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer system on the receiving end. By utilizing two related clock signals, one clock signal being an integer multiple of the other, a self-synchronizing serializer/deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.

Abstract translation: 公开了一种用于改善计算机系统的通信能力的装置和方法。 本发明最优选的实施例使用一系列数据缓冲器和数据寄存器来处理输入的高速数据信号。 通过使用缓冲器和寄存器，输入信号可以以比原始传输频率低得多的频率重新格式化和操纵。 本发明的解串器还比通常采样输入数据信号的更大部分以进一步提高可靠性。 本发明的这些各种特征提供了更稳定和可靠的通信链路，并且还将提供用于序列化/反序列化的较便宜的解决方案。 本发明包括串行器，其接收从计算机输入的并行数据，并且串行化数据以通过高速串行通信链路传输。 在接收端，本发明提供一种解串器，其可以将串行数据快速有效地转换成并行形式，以在接收端的计算机系统内使用。 通过利用两个相关的时钟信号，一个时钟信号是另一个的整数倍，可以创建自同步串行器/解串器。 另外，通过增加接收端的数据样本的大小，从串行传输中检索并行信号所需的比较可以以比串行传输的频率低得多的频率进行。 在最优选的实施例中，本发明作为在外围部件互连（PCI）卡上制造的集成解决方案提供，从而允许本发明容易地安装到现有的计算机系统中。

公开(公告)号：US06218969B1

公开(公告)日：2001-04-17

申请号：US09372344

申请日：1999-08-11

Applicant: Lynn R. Watson ,  James E. Castleberry ,  David D. Luke ,  David C. Gilbert

Inventor： Lynn R. Watson ,  James E. Castleberry ,  David D. Luke ,  David C. Gilbert

IPC: H03M900

CPC classification number: H03M9/00

Abstract: A serial to parallel port signal converter for interconnection between a hosts utilizing Uniform Serial Bus communications protocols and a peripheral device uses IEEE 1284 complaint communications protocol. The signal converter appears to the host as a fully compliant bi-directional USB device, and to the peripheral device as a fully compliant IEEE 1284 host.

Abstract translation: 使用统一串行总线通信协议的主机和外围设备之间的互连的串行到并行端口信号转换器使用IEEE 1284投诉通信协议。 信号转换器作为完全兼容的双向USB设备向主机显示，作为完全符合IEEE 1284主机的外设。