公开(公告)号：US07459939B2

公开(公告)日：2008-12-02

申请号：US10569156

申请日：2004-09-09

Applicant: William John Testin ,  David Gene Novak

Inventor： William John Testin ,  David Gene Novak

IPC: H03K19/175

CPC classification number: G06F13/4086 ,  G06F13/4077 ,  H03K19/0016

Abstract: An active pull up configuration for data bus lines unaffected by integral pull up resistors within subsystems. The present application generally relates to digital systems comprising a plurality of power supply levels and data buses. More particularly, this invention relates to digital system comprising subsystems connected by common buses that require automatic charging of certain buses or lines. In a television signal processing apparatus using an I2C bus and using the present invention according to a exemplary embodiment of the present invention, a first device operative in a first mode of operation and a second device operative in said first mode of operation and a second mode of operation wherein said first circuit and said second circuit are both connected by the I2C bus wherein said each data bus line requiring an active pull up is connected to a first power supply via a first resistor integrated within the first device and connected to a second power supply via a second resistor integrated within said second device. The first resistor is electrically isolated from the first power supply during the second mode of operation and electrically connected to the first power supply during the second mode of operation.

Abstract translation: 数据总线的主动上拉配置，不受子系统内的整合上拉电阻的影响。 本申请通常涉及包括多个电源电平和数据总线的数字系统。 更具体地说，本发明涉及数字系统，其包括由需要对某些总线或线路进行自动充电的公共总线连接的子系统。 在根据本发明的示例性实施例的使用I2C总线并使用本发明的电视信号处理装置中，在第一操作模式下操作的第一装置和在所述第一操作模式下操作的第二装置和第二模式 其中所述第一电路和所述第二电路都通过I2C总线连接，其中所述每个需要主动上拉的数据总线线路经由集成在第一设备内的第一电阻器连接到第一电源，并连接到第二电源 通过集成在所述第二装置内的第二电阻供应。 第一电阻器在第二操作模式期间与第一电源电隔离，并且在第二操作模式期间电连接到第一电源。

公开(公告)号：US07312636B2

公开(公告)日：2007-12-25

申请号：US11347289

申请日：2006-02-06

Applicant: Valerie L. Lines

Inventor： Valerie L. Lines

IPC: H03K19/175

CPC classification number: H03K19/018521 ,  G11C8/08 ,  G11C11/4085 ,  H03K19/0013

Abstract: A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low supply voltage levels. The disclosed level shifter is configured such that the size of the preceding logic gate and circuitry within the level shifter can be reduced, facilitating its layout in pitch-limited areas. The level shifter also includes circuitry to decouple the output pull-up and pull-down paths to further facilitate state transitions and reduce crowbar current consumption.

Abstract translation: 一种电平移位器电路，用于将具有第一高电平和低电源电平电平的逻辑“1”和“0”电平的逻辑信号转换为具有第二高电平和低电源电平的信号。 特别地，第二高和低电源电压电平大于第一高和低电源电压电平。 所公开的电平移位器被配置为使得可以减小电平移位器内的前一逻辑门和电路的尺寸，便于其在音高限制区域中的布局。 电平移位器还包括用于去耦输出上拉和下拉路径的电路，以进一步促进状态转换并减少撬棒电流消耗。

公开(公告)号：US07176710B1

公开(公告)日：2007-02-13

申请号：US11093188

申请日：2005-03-28

Applicant: Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

Inventor： Mei Luo ,  Wilson Wong ,  Sergey Shumarayev

IPC: H03K19/175

CPC classification number: H04L25/0278

Abstract: The on-chip impedance termination circuits can be dynamically adjusted to match transmission line impedance values. A network of termination resistors on an integrated circuit provides termination impedance to a transmission line coupled to an IO pin. The termination resistors are coupled in series and in parallel with each other. Pass gates are coupled to the resistors. The pass gates are individually turned ON or OFF to couple or decouple resistors from the transmission line. Each pass gate is set to be ON or OFF to provide a selected termination resistance value to the transmission line. The termination resistance of the resistor network can be increased or decreased to match the impedance of different transmission lines. The termination resistance can also be varied to compensate for changes in the resistors caused by temperature variations on the integrated circuit or other factors.

Abstract translation: 片内阻抗终端电路可以动态调节，以匹配传输线阻抗值。 集成电路上的终端电阻网络为耦合到IO引脚的传输线提供终端阻抗。 终端电阻器串联耦合并且彼此并联。 通孔与电阻耦合。 传递门单独接通或断开以将电阻与传输线耦合或去耦。 每个通过门被设置为ON或OFF以向传输线提供所选择的终端电阻值。 可以增加或减少电阻网络的终端电阻以匹配不同传输线路的阻抗。 也可以改变终端电阻以补偿由集成电路上的温度变化或其他因素引起的电阻器的变化。

公开(公告)号：US06940310B2

公开(公告)日：2005-09-06

申请号：US10673756

申请日：2003-09-29

Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

IPC: G11C7/10 ,  H03K17/00 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/175

CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

Abstract translation: 讨论了抑制低压集成电路中的薄栅氧化物晶体管的半导体击穿的输入缓冲器。 输入缓冲器的一个方面包括具有栅极，漏极和源极的输入级。 输入级的门接受禁止信号，漏极接受输入信号。 当禁止信号处于预定电平时，输入级禁止在输入级的源处呈现输入信号。 输入缓冲器还包括具有包括第一连接和第二连接的逆变器的输出级。 第一连接耦合到输入级的源极，第二连接将输入信号提供给低压闪存器件。

公开(公告)号：US06900664B2

公开(公告)日：2005-05-31

申请号：US10319141

申请日：2002-12-12

Applicant: Leon Wu

Inventor： Leon Wu

IPC: G11C7/10 ,  G11C11/4093 ,  H03K19/175

CPC classification number: G11C11/4093 ,  G11C7/10

Abstract: A preferred embodiment includes a distributed network of a plurality of dynamically configurable bi-directional input/output (I/O) cells, each including a forward datapath having a first receiver, for receiving a first input signal from downstream driver on a first port of a signal line, coupled to a first driver for sending a first output signal to a first upstream receiver on a second port of the signal line; and a reverse datapath having a second receiver, for receiving a second input signal from a second downstream driver on the second port of the signal line, coupled to a second driver for sending a second output signal to a second upstream receiver on the first port of the signal line; wherein the first input signal and the second output signal are transmitted concurrently on the first port of the signal line.

Abstract translation: 优选实施例包括多个动态可配置的双向输入/输出（I / O）单元的分布式网络，每个单元包括具有第一接收器的前向数据路径，用于在第一端口的第一端口处接收来自下游驱动器的第一输入信号 信号线，耦合到第一驱动器，用于向所述信号线的第二端口上的第一上游接收器发送第一输出信号; 以及具有第二接收器的反向数据路径，用于从信号线的第二端口上的第二下游驱动器接收第二输入信号，耦合到第二驱动器，用于将第二输出信号发送到第一端口上的第二上游接收器 信号线; 其中所述第一输入信号和所述第二输出信号在所述信号线的第一端口上同时发送。

公开(公告)号：US5811984A

公开(公告)日：1998-09-22

申请号：US539581

申请日：1995-10-05

Applicant: Stephen I. Long ,  Qi Zhang

Inventor： Stephen I. Long ,  Qi Zhang

IPC: H03K19/0185 ,  H04L25/02 ,  H03K17/16 ,  H03K19/175

CPC classification number: H03K19/018557 ,  H04L25/0278 ,  H04L25/0282 ,  H04L25/0294

Abstract: A digital input/output interface for use with two digital circuits connected by a transmission line having a characteristic impedance Z.sub.0 includes a current driver in one of the digital circuits and a current receiver in the other digital circuit. The current driver is configured to generate a current in the transmission line when a digital signal is applied to the current driver. The current receiver includes a current conversion element connected to the transmission line at an input node through an input impedance Z.sub.in and adapted to convert the current in the transmission line into an output voltage, and an active termination element configured to actively adjust the input impedance Z.sub.in to match the characteristic impedance Z.sub.0 of the transmission line. An impedance transforming receiver for use with a transmission line having a small characteristic impedance Z.sub.0 and carrying a relatively small current mode signal includes the following: an input element connected to the transmission line and configured to receive the small current mode signal, the input element having a small input impedance Z.sub.in that substantially matches the characteristic impedance of the transmission line; and a high impedance output element adapted to convert the small current mode signal into an output binary voltage having a noise margin large enough for digital communication.

Abstract translation: 用于通过具有特性阻抗Z0的传输线连接的两个数字电路的数字输入/输出接口包括数字电路之一中的电流驱动器和另一数字电路中的电流接收器。 当数字信号被施加到当前驱动器时，当前驱动器被配置为在传输线中产生电流。 电流接收器包括电流转换元件，其通过输入阻抗Zin连接到输入节点处的传输线，并且适于将传输线中的电流转换为输出电压;以及主动终端元件，其被配置为主动调整输入阻抗Zin 以匹配传输线的特性阻抗Z0。 用于具有小特征阻抗Z0并且承载相对小的电流模式信号的传输线的阻抗变换接收器包括：连接到传输线并被配置为接收小电流模式信号的输入元件，该输入元件具有 基本上匹配传输线的特性阻抗的小的输入阻抗Zin; 以及高阻抗输出元件，适于将小电流模式信号转换成具有足够数字通信的噪声容限的输出二进制电压。

公开(公告)号：US07222208B1

公开(公告)日：2007-05-22

申请号：US09644463

申请日：2000-08-23

Applicant: Matthew B. Haycock ,  Amaresh Pangal

Inventor： Matthew B. Haycock ,  Amaresh Pangal

IPC: G06F1/00 ,  H03K19/175

CPC classification number: G06F13/4077

Abstract: A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance, and includes a receiver with input hysteresis. The input hysteresis of the receiver is not satisfied unless both drivers with imbalanced output impedance coupled to the bus assert an output signal. Each driver asserts a signal on the bus when initialization of the corresponding simultaneous bidirectional port is complete. When both simultaneous bidirectional ports are initialized, the hysteresis of the receivers is satisfied, and each port is notified that both have been initialized.

Abstract translation: 耦合到总线的同时双向端口包括同步电路，该同步电路使端口与耦合到同一总线的另一同时数据端口同步。 同步电路包括具有不平衡输出阻抗的输出驱动器，并且包括具有输入滞后的接收器。 接收器的输入滞后不能满足，除非与总线耦合的不平衡输出阻抗的驱动器都断言输出信号。 当对应的同时双向端口的初始化完成时，每个驱动器在总线上断言信号。 当两个同时双向端口被初始化时，接收器的滞后被满足，并且通知两个端口都被初始化。

公开(公告)号：US07098694B2

公开(公告)日：2006-08-29

申请号：US10988103

申请日：2004-11-12

Applicant: Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris

Inventor： Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris

IPC: H03K19/175

CPC classification number: H03K19/00315

Abstract: When a P-channel pass gate transistor is added in parallel to an N-channel pass gate, the resulting circuit improves overvoltage tolerance of an input buffer. A simple bias circuit including two small transistors controls a gate of this P-channel pass gate transistor in such a way that it is turned OFF when an overvoltage is applied, but turned ON when a normal voltage is applied. Another embodiment has two N-channel devices (M12, M13) coupled in series with each other and one of the N-channel devices (M13) being configured in a “turned off” position, by coupling the source and gate terminals to a ground voltage (VSS) and providing the supply voltage (VDD) at the gate terminal of another N-channel device (M12), whereby the device M12 protects the device M13 from overvoltage.

Abstract translation: 当P沟道栅极晶体管与N沟道栅极并联并联时，得到的电路提高了输入缓冲器的过压容差。 包括两个小晶体管的简单偏置电路以这样的方式控制该P沟道栅极晶体管的栅极，使得当施加过电压时其被截止，而当施加正常电压时，该栅极导通。 另一个实施例具有彼此串联耦合的两个N沟道器件（M12，M13），并且N沟道器件（M13）中的一个被配置为处于“截止”位置，通过将源极和栅极端子 接地电压（VSS），并在另一N沟道器件（M12）的栅极端提供电源电压（VDD），由此器件M 12保护器件M 13免受过压。

公开(公告)号：US07057415B2

公开(公告)日：2006-06-06

申请号：US10732695

申请日：2003-12-10

Applicant: Andrew R. Allen ,  Barry J. Arnold

Inventor： Andrew R. Allen ,  Barry J. Arnold

IPC: H03K19/175

CPC classification number: H03K19/00369

Abstract: One or more characteristics of circuitry for an output buffer are identified relative to a reference a plurality of times to produce a sequence of results. One or more compensation signals for one or more output buffers are generated based on results satisfying one or more conditions.

Abstract translation: 用于输出缓冲器的电路的一个或多个特性相对于参考多次被识别以产生一系列结果。 基于满足一个或多个条件的结果生成一个或多个输出缓冲器的一个或多个补偿信号。

公开(公告)号：US07053659B2

公开(公告)日：2006-05-30

申请号：US10818571

申请日：2004-04-06

Applicant: Robert R. Livolsi ,  Wayne L. Gerber ,  Carlos I. Gomez

Inventor： Robert R. Livolsi ,  Wayne L. Gerber ,  Carlos I. Gomez

IPC: H03K19/175

CPC classification number: H03K19/018521 ,  H03K19/01707

Abstract: Rapid switching is provided by a circuit that controls the current passing through a chain of CMOS devices arranged in a series circuit. A node output terminal to the circuit is provided intermediate the chain to control the partially conductive state of two other CMOS devices. Voltages at the output terminal sets one or the other of the two CMOS devices in the current conducting state. That state is a partially conducting state of the CMOS device so that small changes flowing in the current path allows a quick transfer of the operating state to the other device. With this arrangement, discharging of large capacitances is avoided by using the small current changes to rapidly switch between the partially conducting CMOS devices.

Abstract translation: 快速切换由控制通过串联电路中布置的CMOS器件链的电流的电路提供。 提供到电路的节点输出端子在链路之间，以控制两个其它CMOS器件的部分导通状态。 在输出端子处的电压将两个CMOS器件中的一个或另一个设置为当前导通状态。 该状态是CMOS器件的部分导通状态，使得在当前路径中流动的小变化允许将操作状态快速传送到另一个器件。 通过这种布置，通过使用小的电流变化来避免在部分导电的CMOS器件之间快速切换的大电容的放电。