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    Enhanced protection for input buffers of low-voltage flash memories
    1.
    发明授权
    Enhanced protection for input buffers of low-voltage flash memories 失效
    增强对低压闪存输入缓冲器的保护

    公开(公告)号：US06940310B2

    公开(公告)日：2005-09-06

    申请号：US10673756

    申请日：2003-09-29

    Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    IPC: G11C7/10 ,  H03K17/00 ,  H03K17/08 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/175

    CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

    Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

    Abstract translation: 讨论了抑制低压集成电路中的薄栅氧化物晶体管的半导体击穿的输入缓冲器。 输入缓冲器的一个方面包括具有栅极，漏极和源极的输入级。 输入级的门接受禁止信号，漏极接受输入信号。 当禁止信号处于预定电平时，输入级禁止在输入级的源处呈现输入信号。 输入缓冲器还包括具有包括第一连接和第二连接的逆变器的输出级。 第一连接耦合到输入级的源极，第二连接将输入信号提供给低压闪存器件。

    Enhanced protection for input buffers of low-voltage flash memories
    3.
    发明授权
    Enhanced protection for input buffers of low-voltage flash memories 失效

    公开(公告)号：US07057416B2

    公开(公告)日：2006-06-06

    申请号：US11003676

    申请日：2004-12-03

    Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    IPC: H03K19/175

    CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

    Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

    Enhanced protection for input buffers of low-voltage flash memories
    4.
    发明授权
    Enhanced protection for input buffers of low-voltage flash memories 有权
    增强对低压闪存输入缓冲器的保护

    公开(公告)号：US06628142B1

    公开(公告)日：2003-09-30

    申请号：US09651478

    申请日：2000-08-30

    Applicant: Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    Inventor： Giulio-Giuseppe Marotta ,  Elio D'Ambrosio

    IPC: H03K19175

    CPC classification number: G11C7/1084 ,  G11C7/1078 ,  G11C2207/2227 ,  H03K19/00315

    Abstract: An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.

    Abstract translation: 讨论了抑制低压集成电路中的薄栅氧化物晶体管的半导体击穿的输入缓冲器。 输入缓冲器的一个方面包括具有栅极，漏极和源极的输入级。 输入级的门接受禁止信号，漏极接受输入信号。 当禁止信号处于预定电平时，输入级禁止在输入级的源处呈现输入信号。 输入缓冲器还包括具有包括第一连接和第二连接的逆变器的输出级。 第一连接耦合到输入级的源极，第二连接将输入信号提供给低压闪存器件。

    On-chip temperature sensor
    7.
    发明授权
    On-chip temperature sensor 有权
    片上温度传感器

    公开(公告)号：US07978556B2

    公开(公告)日：2011-07-12

    申请号：US12613139

    申请日：2009-11-05

    Applicant: Agostino Macerola ,  Giulio-Giuseppe Marotta ,  Marco-Domenico Tiburzi

    Inventor： Agostino Macerola ,  Giulio-Giuseppe Marotta ,  Marco-Domenico Tiburzi

    IPC: G11C7/04

    CPC classification number: G01K7/01 ,  G01K2219/00 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626

    Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n−1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n−1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

    Abstract translation: 产生温度不变参考电压和温度变化的物理量，例如电压或电流。 温度变化的物理量响应于集成电路的温度而变化。 温度传感器电路产生与温度成线性关系的电压。 电平发生器电路从参考电压产生2n-1个电压电平。 比较器电路，例如模拟 - 数字电路，将来自温度传感器的电压与2n-1个电压电平进行比较，以确定哪个电平最接近。 所得电平的n位数字输出与集成电路的温度成比例。

    On-chip temperature sensor
    8.
    发明授权
    On-chip temperature sensor 有权
    片上温度传感器

    公开(公告)号：US07630265B2

    公开(公告)日：2009-12-08

    申请号：US11891949

    申请日：2007-08-14

    Applicant: Agostino Macerola ,  Giulio-Giuseppe Marotta ,  Marco-Domenico Tiburzi

    Inventor： Agostino Macerola ,  Giulio-Giuseppe Marotta ,  Marco-Domenico Tiburzi

    IPC: G11C7/04

    CPC classification number: G01K7/01 ,  G01K2219/00 ,  G11C7/04 ,  G11C11/406 ,  G11C11/40626

    Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n−1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n−1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

    Abstract translation: 产生温度不变参考电压和温度变化的物理量，例如电压或电流。 温度变化的物理量响应于集成电路的温度而变化。 温度传感器电路产生与温度成线性关系的电压。 电平发生器电路从参考电压产生2n-1个电压电平。 比较器电路，例如模拟 - 数字电路，将来自温度传感器的电压与2n-1电压电平进行比较，以确定哪个电平最接近。 所得电平的n位数字输出与集成电路的温度成比例。

    Memory cell sensing using negative voltage
    9.
    发明授权
    Memory cell sensing using negative voltage 有权
    存储单元感应使用负电压

    公开(公告)号：US08614923B2

    公开(公告)日：2013-12-24

    申请号：US13426075

    申请日：2012-03-21

    Applicant: Agostino Macerola ,  Giulio-Giuseppe Marotta

    Inventor： Agostino Macerola ,  Giulio-Giuseppe Marotta

    IPC: G11C5/14

    CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30

    Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

    Abstract translation: 本公开的实施例提供了使用负电压的存储器单元感测的方法，装置，模块和系统。 一种方法包括将负的读取电压施加到存储器单元阵列的所选择的存取线，向阵列的多个未选择的存取线施加通过电压，以及感测耦合到所选择的存取线的单元是否处于导通状态 响应于所施加的负读电压。

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