公开(公告)号：US6140837A

公开(公告)日：2000-10-31

申请号：US161192

申请日：1998-09-25

Applicant: David D. Eaton ,  Richard J. Wong ,  James M. Apland

Inventor： David D. Eaton ,  Richard J. Wong ,  James M. Apland

IPC: H01L21/8234 ,  H01L27/118 ,  H03K19/173 ,  G05F1/10 ,  H03K19/175

CPC classification number: H01L21/823462 ,  H01L27/11807

Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers. In some embodiments, the second power input terminal receives a voltage higher than the first supply voltage during antifuse programming such that the oscillating signal that drives the charge pumps has a larger amplitude thereby allowing back bias threshold voltages of transistors in the charge pumps to be overcome, facilitating starting of the charge pumps, and/or increasing charge pump efficiency.

Abstract translation: 可编程器件具有采用反熔丝的数字逻辑元件和可编程互连结构，反熔丝是可编程的，以将选定的数字逻辑元件连接在一起。 在正常电路操作期间，使用第一电力输入端子以在第一电力输入端子上接收的第一电源电压为数字逻辑元件供电。 在正常电路操作期间，使用第二电力输入端子来保护可编程器件的电路免受可编程器件外部的电路驱动到可编程器件的端子的高电压信号。 在反熔丝编程期间，第二电源输入端用于驱动编程驱动器和/或编程控制驱动器的电荷泵。 在一些实施例中，第二电力输入端子在反熔丝编程期间接收高于第一电源电压的电压，使得驱动电荷泵的振荡信号具有较大的幅度，从而允许克服电荷泵中晶体管的反向偏置阈值电压 ，促进电荷泵的启动和/或增加电荷泵效率。

公开(公告)号：US5544070A

公开(公告)日：1996-08-06

申请号：US937331

申请日：1992-08-27

Applicant: William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

Inventor： William D. Cox ,  Andrew K. L. Chan ,  Richard J. Wong ,  James M. Apland ,  Kathryn E. Gordon

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H03K19/177

CPC classification number: H03K19/17764 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H03K19/17704 ,  H03K19/1778 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.

Abstract translation: 可编程器件包括用第一编程方法编程的第一反熔丝和用第二编程方法编程的第二反熔丝，由此流过第二反熔丝的实际工作电流超过第一反熔丝的最大允许工作电流但不超过最大值 第二反熔丝的允许工作电流，由此流过第一反熔丝的实际工作电流不超过第一反熔丝的最大允许工作电流，由此流过第二反熔丝的实际工作电流不超过最大允许工作电流 的第二个反熔丝。 通过允许在一些反熔丝上使用编程方法来编程其他抗反熔丝，对于现场可编程器件中的用户特定电路的实现是有利的，并且在现场可编程器件中实现的用户特定电路的可靠性是 增强。

公开(公告)号：US6097077A

公开(公告)日：2000-08-01

申请号：US75493

申请日：1998-05-08

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  Y10S148/055

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract translation: 公开了具有抗熔丝的防潮和门阵列，其具有高的热稳定性，减小的尺寸，减小的漏电流，在未编程状态下的减小的电容，改善的制造产量和更可控的电特性。 一些反熔丝包括反熔丝通孔中的间隔物。 在一些反熔丝中，可编程材料是平面的，并且顶部或底部电极形成在反熔丝通孔中。 在一些栅极阵列中，反熔丝形成在介电分离两层布线通道之上，而不是在该介电层之下。

公开(公告)号：US5362676A

公开(公告)日：1994-11-08

申请号：US920971

申请日：1992-07-28

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L21/768 ,  H01L23/525 ,  H01L21/283

CPC classification number: H01L23/5252 ,  H01L21/76888 ,  H01L2924/0002

Abstract: An amorphous silicon antifuse has a bottom electrode, a dielectric overlying the bottom electrode, amorphous silicon contacting the bottom electrode in a via in the dielectric, and the top electrode over the amorphous silicon. Spacers are provided in the via corners between the amorphous silicon and the top electrode. The spacers smooth the surface above the amorphous silicon, provide good top electrode step coverage, and reduce leakage current. Another amorphous silicon antifuse is provided in which the amorphous silicon layer is planar. The planarity makes the amorphous silicon layer easy to manufacture. A programmable CMOS circuit is provided in which the antifuses are formed over the intermetal dielectric. The antifuses are not affected by the high temperatures associated with the formation of the intermetal dielectric and the first-metal contacts. The intermetal dielectric protects the circuit elements during the antifuse formation. The bottom electrodes of the antifuses are connected to the first-metal contacts. The overall capacitance associated with the antifuses is low, and hence the circuit is fast.

Abstract translation: 非晶硅反熔丝具有底部电极，覆盖底部电极的电介质，与电介质中的通孔中的底部电极接触的非晶硅以及无定形硅上的顶部电极。 隔板设置在非晶硅和顶部电极之间的通孔拐角处。 间隔物平滑无定形硅上方的表面，提供良好的顶部电极台阶覆盖，并减少漏电流。 提供另一种非晶硅反熔丝，其中非晶硅层是平面的。 平面度使得非晶硅层容易制造。 提供了可编程CMOS电路，其中在金属间电介质上形成反熔丝。 反熔丝不受与金属间电介质和第一金属触点的形成相关的高温的影响。 金属间介质在反熔丝形成期间保护电路元件。 反熔丝的底部电极连接到第一金属触点。 与反熔丝相关的总电容低，因此电路快。

公开(公告)号：US6028444A

公开(公告)日：2000-02-22

申请号：US771471

申请日：1996-12-20

Applicant: Richard J. Wong ,  Paige A. Kolze

Inventor： Richard J. Wong ,  Paige A. Kolze

IPC: H02H9/00 ,  H03K17/22 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K17/223 ,  H03K19/1778

Abstract: Internal net drivers of a field programmable gate array are laid out with additional transistors to increase current drive capability at low supply voltages when a low supply voltage mask option is used. When a high supply voltage mask option is used, the additional transistors are not used in this way and the net drivers do not provide additional switching current drive capability. In some embodiments, were a low supply voltage mask option net driver operated at the high supply voltage, an impermissibly large switching current would flow through a programmed antifuse in a net coupled to the output of the net driver.

Abstract translation: 当使用低电源电压掩模选项时，现场可编程门阵列的内部网络驱动器布置有额外的晶体管，以在低电源电压下增加电流驱动能力。 当使用高电源电压掩模选项时，不以这种方式使用附加晶体管，并且网络驱动器不提供额外的开关电流驱动能力。 在一些实施例中，是在高电源电压下操作的低电源电压掩模选项网络驱动器，不可允许的大开关电流将流过耦合到网络驱动器的输出的网络中的经编程的反熔丝。

公开(公告)号：US5557136A

公开(公告)日：1996-09-17

申请号：US892466

申请日：1992-06-01

Applicant: Kathryn E. Gordon ,  Richard J. Wong

Inventor： Kathryn E. Gordon ,  Richard J. Wong

IPC: H01L23/525 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

公开(公告)号：US5293133A

公开(公告)日：1994-03-08

申请号：US937071

申请日：1992-08-27

Applicant: John M. Birkner ,  David T. Martin ,  Richard J. Wong

Inventor： John M. Birkner ,  David T. Martin ,  Richard J. Wong

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/50

CPC classification number: G11C29/027 ,  G11C17/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50008 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A method for determining an electrical characteristic (such as a resistance) of an antifuse of a programmable device. The method comprises the steps of: 1) before the antifuse is programmed, determining an electrical characteristic (such as a voltage, current and/or resistance) of a first conductive path which includes a series element disposed electrically in series with a parallel element, the parallel element being controlled to be substantially conductive, the parallel element being disposed electrically in parallel with the unprogrammed antifuse; 2) after programming of the antifuse, determining an electrical characteristic (such as a voltage, current and/or resistance) of a second conductive path including the series element disposed electrically in series with the programmed antifuse when the parallel element is controlled to be substantially nonconductive; 3) determining an electrical characteristic (such as a voltage, current and/or resistance) of a third, conductive path through the series element, and through the programmed antifuse and the parallel element, the parallel element being controlled to be substantially conductive; and 4) determining the electrical characteristic (such as a resistance) of the antifuse based on the above three determinations in 1), 2) and 3). The method is usable to determine whether or not programmed antifuses of a programmable device have low enough resistances to meet desired reliability criteria.

Abstract translation: 一种用于确定可编程器件的反熔丝的电特性（例如电阻）的方法。 该方法包括以下步骤：1）在对反熔丝进行编程之前，确定第一导电路径的电特性（例如电压，电流和/或电阻），其包括与并联元件串联设置的串联元件， 所述并联元件被控制为基本导电，所述并联元件与所述未编程的反熔丝电平行地布置; 2）在对反熔丝进行编程之后，确定包括串联元件的第二导电路径的电特性（例如电压，电流和/或电阻），该第二导电路径包括与编程的反熔丝串联设置的串联元件， 非导电; 3）确定通过串联元件的第三导电路径的电特性（例如电压，电流和/或电阻），以及通过编程的反熔丝和并联元件，所述并联元件被控制为基本导电; 以及4）基于上述3）中确定的反熔丝的电特性（如电阻）。 该方法可用于确定可编程器件的编程反熔丝是否具有足够低的电阻以满足期望的可靠性标准。

公开(公告)号：US08547155B2

公开(公告)日：2013-10-01

申请号：US13214681

申请日：2011-08-22

Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

IPC: H03K3/02

CPC classification number: H03K3/0375

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。

公开(公告)号：US20130049835A1

公开(公告)日：2013-02-28

申请号：US13214681

申请日：2011-08-22

Applicant: John C. Holst ,  ShiJie Wen ,  Richard J. Wong

Inventor： John C. Holst ,  ShiJie Wen ,  Richard J. Wong

IPC: H03K3/289

CPC classification number: H03K3/0375

Abstract: A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Abstract translation: 提供锁存装置和相关布局技术以减少由辐射或其他暴露于电离/带电粒子引起的软错误率。 闩锁装置包括形成存储单元的一对交叉耦合的反相器。 一对时钟传输晶体管耦合到该对交叉耦合的反相器。 一对时钟传输晶体管被配置为接收时钟信号作为输入。 在锁存器件的真实和补偿侧，在一对交叉耦合的反相器之一和一对时钟传输晶体管中的一个之间形成沟道连接区域。 每个通道连接区域被配置为具有减小的线性能量传递（LET）横截面。 减少的LET截面导致软错误率降低。

公开(公告)号：US06577017B1

公开(公告)日：2003-06-10

申请号：US09916036

申请日：2001-07-25

Applicant: Richard J. Wong

Inventor： Richard J. Wong

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2224/45099

Abstract: A lower metal plate having a strip-like opening is used in a bond pad structure having metal plugs coupling the lower metal plate to an upper metal plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper metal plate, through the strip-like opening, and to a foundation layer upon which the lower metal plate is disposed. The bond pad structure can be fabricated using the same semiconductor processing steps used to fabricate amorphous silicon antifuse structures having metal plugs.

Abstract translation: 具有带状开口的下部金属板用于具有将下部金属板连接到上部金属板的金属插塞的接合焊盘结构。 填充条状开口之上的体积的相对刚性材料的体积将来自上金属板的应力通过带状开口传递到下金属板所在的基础层。 可以使用用于制造具有金属插塞的非晶硅反熔丝结构的相同的半导体加工步骤来制造接合焊盘结构。