公开(公告)号：US06633182B2

公开(公告)日：2003-10-14

申请号：US09947289

申请日：2001-09-05

Applicant: Larry Pileggi ,  Herman Schmit

Inventor： Larry Pileggi ,  Herman Schmit

IPC: H03K738

CPC classification number: H01L27/118 ,  G06F17/5054

Abstract: A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.

Abstract translation: 一种方法包括将定义FPGA的开关状态的位流转换成一组通孔几何形状，或者直接从物理设计系统生成该组通孔几何形状。 通孔几何形状用于产生至少一个通孔掩模。 然后，在制造过程中使用通孔掩模来定制固定和/或可编程逻辑块阵列。

公开(公告)号：US06542000B1

公开(公告)日：2003-04-01

申请号：US09627576

申请日：2000-07-28

Applicant: William C. Black ,  Bodhisattva Das ,  Marwan M. Hassoun ,  Edward K. F. Lee

Inventor： William C. Black ,  Bodhisattva Das ,  Marwan M. Hassoun ,  Edward K. F. Lee

IPC: H03K738

CPC classification number: G11C14/00 ,  H03K3/356008 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778

Abstract: In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.

Abstract translation: 在本发明中，使用本文公开的锁存器来提出三种非易失FPLD结构方案。 在第一个提出的方案中，可以使用GMR或SDT器件设计的锁存器将在传统的可编程逻辑阵列（PLA）中用作互连。 在第二个提出的方案中，锁存器将构成标准PLA的查找表。 在第三个提出的方案中，锁存器本身将用作非易失性可编程逻辑器件（PLD）结构。 对于n输入逻辑门，该FPLD锁存器将具有2n GMR或SDT电阻，而不仅仅是2。 通过对电阻器编程不同，在每个方案中，可以实现来自相同逻辑门的许多不同的逻辑功能。

公开(公告)号：US06646466B1

公开(公告)日：2003-11-11

申请号：US10011936

申请日：2001-12-05

Applicant: Alan J. Coppola ,  Joel Stanley ,  Steven J. E. Wilton

Inventor： Alan J. Coppola ,  Joel Stanley ,  Steven J. E. Wilton

IPC: H03K738

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: A method and architecture for providing signal paths between a programmable logic core and a fixed function core comprising the steps of (a) coupling one or more first signals between the fixed function core and an interface block configured to couple the fixed function core and the programmable logic core and (b) coupling one or more second signals between the interface block and the programmable logic core.

Abstract translation: 一种用于在可编程逻辑核心和固定功能核心之间提供信号路径的方法和架构，包括以下步骤：（a）将所述固定功能核心与被配置为将所述固定功能核心和所述可编程 逻辑核心和（b）在接口块和可编程逻辑核之间耦合一个或多个第二信号。

公开(公告)号：US06236229B1

公开(公告)日：2001-05-22

申请号：US09310962

申请日：1999-05-13

Applicant: Zvi Or-Bach

Inventor： Zvi Or-Bach

IPC: H03K738

CPC classification number: H03K19/17796 ,  H03K19/17728

Abstract: A semiconductor device including a logic array having a multiplicity of identical logic cells, each identical logic cell comprising at least one look-up table, a metal connection layer overlying the multiplicity of identical logic cells for providing a permanent customized interconnect between various inputs and outputs thereof.

Abstract translation: 一种包括具有多个相同逻辑单元的逻辑阵列的半导体器件，每个相同的逻辑单元包括至少一个查找表，覆盖多个相同逻辑单元的金属连接层，用于提供各种输入和输出之间的永久定制互连 其中。

公开(公告)号：US06426649B1

公开(公告)日：2002-07-30

申请号：US09751440

申请日：2000-12-29

Applicant: Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

Inventor： Robert Fu ,  David D. Eaton ,  Kevin K. Yee ,  Andrew K. Chan

IPC: H03K738

CPC classification number: H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/1778 ,  H03L7/183

Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

Abstract translation: 现场可编程门阵列包括可编程互连结构和多个逻辑单元。 每个逻辑单元包括与可编程互连结构具有直接互连的多个组合逻辑电路，以及用作寄存器的多个顺序逻辑元件，例如D型触发器。 组合逻辑电路可以直接连接到可编程互连结构，并且连接到顺序逻辑元件的输入端。 因此，逻辑单元包括与可编程互连结构的组合和注册连接。 此外，顺序元件之一可以选择性地从可编程互连结构接收专用输入。 逻辑单元的输出引线通过包括保护晶体管的驱动器连接到可编程互连结构。 保护晶体管的栅极耦合到与多个驱动器共享的主电荷泵以及与驱动器相关联的次级电荷泵。

公开(公告)号：US06384627B1

公开(公告)日：2002-05-07

申请号：US09788062

申请日：2001-02-16

Applicant: Bradley K. Fross ,  Edward S. McGettigan

Inventor： Bradley K. Fross ,  Edward S. McGettigan

IPC: H03K738

CPC classification number: H03K19/17752 ,  G06F7/02 ,  G06F7/026 ,  H03K19/1736 ,  H03K19/17756

Abstract: A method of configuring an FPGA lookup table to implement both exact and relative matching comparators is disclosed. Examples of exact matching of two variables, exact matching of a variable to a constant, relative matching (greater than) of a variable to a constant, and combined exact and relative matching are discussed. Use of the comparator to trigger a logic analyzer to collect data is discussed.

Abstract translation: 公开了一种配置FPGA查找表以实现精确和相对匹配比较器的方法。 讨论了两个变量的精确匹配，变量与常量的精确匹配，变量与常数的相对匹配（大于），以及精确和相对匹配的组合。 讨论了使用比较器触发逻辑分析仪来收集数据。

公开(公告)号：US06538468B1

公开(公告)日：2003-03-25

申请号：US09629916

申请日：2000-07-31

Applicant: Michael T. Moore

Inventor： Michael T. Moore

IPC: H03K738

CPC classification number: G06F9/4411 ,  H03K19/1776 ,  H03K19/17772 ,  H03K19/17796

Abstract: According to one embodiment, a programmable logic assembly (200) may include a nonvolatile memory devices (202-0 and 202-1) coupled to an associated volatile programmable logic device (PLD) (204). Each nonvolatile memory device (202-0 and 202-1) may store different configuration data for a volatile PLD (204). Upon a predetermined event, such as powerup or reset, one of the nonvolatile memory devices (202-0 and 202-1) may be selected and its configuration data read into a volatile PLD (204).

Abstract translation: 根据一个实施例，可编程逻辑组件（200）可以包括耦合到相关联的易失性可编程逻辑器件（PLD）（204）的非易失性存储器件（202-0和202-1）。 每个非易失性存储器件（202-0和202-1）可以存储用于易失性PLD（204）的不同配置数据。 在诸如上电或复位的预定事件之后，可以选择非易失性存储器件（202-0和202-1）中的一个，并将其配置数据读入易失性PLD（204）。

公开(公告)号：US06507214B1

公开(公告)日：2003-01-14

申请号：US09909045

申请日：2001-07-18

Applicant: Warren Snyder

Inventor： Warren Snyder

IPC: H03K738

CPC classification number: G06F1/32 ,  G06F1/08 ,  G06F15/7867 ,  G06G7/06 ,  H03B5/364 ,  H03K3/012 ,  H03K3/014 ,  H03K3/02315

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract translation: 描述了一种新的数字可配置宏架构。 数字可配置宏架构非常适合微控制器或控制器设计。 特别地，数字可配置宏架构的基础是可编程数字电路块。 在一个实施例中，可编程数字电路块是8位电路模块，其可以被编程为通过改变其中的几个寄存器的内容来执行各种预定数字功能中的任何一个，这不同于作为通用设备的FPGA 被编程为执行任意数字功能。 具体地，可编程数字电路块的电路部件被设计为在几个预定的数字功能中重用，以使可编程数字电路块的尺寸最小化。

公开(公告)号：US06211697B1

公开(公告)日：2001-04-03

申请号：US09318198

申请日：1999-05-25

Applicant: Jung-Cheun Lien ,  Sheng Feng ,  Chung-yuan Sun ,  Eddy Chieh Huang

Inventor： Jung-Cheun Lien ,  Sheng Feng ,  Chung-yuan Sun ,  Eddy Chieh Huang

IPC: H03K738

CPC classification number: H03K19/1735 ,  H03K7/04 ,  H03K19/17732 ,  H03K19/17796

Abstract: An integrated circuit (IC) includes both a field-programmable gate array (FPGA) and a hard array (HA). The FPGA includes a first set of functional groups that each include an underlying logic structure and memory cells for programming the underlying logic structure, a first set of routing buses, and a first set of routing interconnect areas that provide interconnections between the first set of functional groups and the first set of routing buses. The first set of routing interconnect areas includes transistors and memory cells for programming the interconnections. The HA includes a second set of functional groups that is equal in number to the first set of functional groups and that are arranged like the first set of functional groups. Each functional group in the second set of functional groups includes an underlying logic structure that is like the underlying logic structure of the first set of functional groups but which does not include memory cells for programming the underlying logic structure. The HA also includes a second set of routing buses that are arranged like the first set of routing buses and a second set of routing interconnect areas that are arranged like the first set of routing interconnect areas but which do not include transistors and memory cells for programming interconnections.

Abstract translation: 集成电路（IC）包括现场可编程门阵列（FPGA）和硬阵列（HA）。 FPGA包括第一组功能组，每组包括底层逻辑结构和用于编程底层逻辑结构的存储单元，第一组路由总线，以及第一组路由互连区域，其提供第一组功能之间的互连 组和第一组路由总线。 第一组路由互连区域包括用于对互连进行编程的晶体管和存储单元。 HA包括第二组功能组，其数量与第一组功能组相同，并且排列成与第一组功能组相同。 第二组功能组中的每个功能组包括底层逻辑结构，其类似于第一组功能组的底层逻辑结构，但不包括用于编程底层逻辑结构的存储单元。 HA还包括第二组路由总线，其布置为类似于第一组路由总线，以及第二组路由互连区域，其布置为类似于第一组路由互连区域，但不包括用于编程的晶体管和存储器单元 互连。

公开(公告)号：US06765407B1

公开(公告)日：2004-07-20

申请号：US10272231

申请日：2002-10-15

Applicant: Warren Snyder

Inventor： Warren Snyder

IPC: H03K738

CPC classification number: G06F1/32 ,  G06F1/08 ,  G06F15/7867 ,  G06G7/06 ,  H03B5/364 ,  H03K3/012 ,  H03K3/014 ,  H03K3/02315

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. In an embodiment, programmable digital circuit blocks are 8-bit circuit modules that can be programmed to perform any one of a variety of predetermined digital functions by changing the contents of a few registers therein, unlike a FPGA which is a generic device that can be programmed to perform any arbitrary digital function. Specifically, the circuit components of the programmable digital circuit block are designed for reuse in several of the predetermined digital functions such that to minimize the size of the programmable digital circuit block.

Abstract translation: 描述了一种新的数字可配置宏架构。 数字可配置宏架构非常适合微控制器或控制器设计。 特别地，数字可配置宏架构的基础是可编程数字电路块。 在一个实施例中，可编程数字电路块是8位电路模块，其可以被编程为通过改变其中的几个寄存器的内容来执行各种预定数字功能中的任何一个，这不同于作为通用设备的FPGA 被编程为执行任意数字功能。 具体地，可编程数字电路块的电路部件被设计为在几个预定的数字功能中重用，以使可编程数字电路块的尺寸最小化。