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    System for substrate potential regulation during power-up in integrated circuits
    2.
    发明授权
    System for substrate potential regulation during power-up in integrated circuits 有权
    集成电路上电期间衬底电位调节系统

    公开(公告)号：US07642835B1

    公开(公告)日：2010-01-05

    申请号：US10712523

    申请日：2003-11-12

    Applicant: Robert Fu ,  Tien-Min Chen

    Inventor： Robert Fu ,  Tien-Min Chen

    IPC: H03K3/01 ,  H01L25/00

    CPC classification number: H01L27/0222 ,  H01L21/823892 ,  H01L29/78 ,  H03K2217/0018

    Abstract: An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

    Abstract translation: 在初始电源施加时，具有由开关协调的体偏置输入的集成电路。 耦合到集成电路的N阱偏压和P型衬底偏置线的开关根据偏置电源线的状态选择性地将衬底耦合到接地或衬底偏置电源。 在上电和初始施加N阱偏压期间，衬底耦合到地，以防止漏极引起衬底电位的上升。 在感测到衬底偏置线上的衬底偏置电位的存在之后，开关将衬底耦合到衬底偏置线而不是接地。 在另一个实施例中，开关通过感测电荷泵使能信号间接地感测到衬底偏置电位的可用性。

    Temperature compensated integrated circuits
    3.
    发明授权
    Temperature compensated integrated circuits 有权
    温度补偿集成电路

    公开(公告)号：US07495497B1

    公开(公告)日：2009-02-24

    申请号：US11125555

    申请日：2005-05-09

    Applicant: Robert Fu

    Inventor： Robert Fu

    IPC: H03K17/687

    CPC classification number: H03K19/00384 ,  H03K3/011 ,  H03K3/0315 ,  H03K17/145

    Abstract: A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.

    Abstract translation: 温度补偿集成电路的方法和系统。 通过应用温度补偿来增强集成电路的工作特性。

    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SELECTIVE COUPLING OF VOLTAGE FEEDS FOR BODY BIAS VOLTAGE IN AN INTEGRATED CIRCUIT DEVICE 有权
    用于集成电路设备中的身体偏置电压的电压馈电的选择性耦合

    公开(公告)号：US20080135905A1

    公开(公告)日：2008-06-12

    申请号：US12033840

    申请日：2008-02-19

    Applicant: James B. Burr ,  Robert Fu

    Inventor： James B. Burr ,  Robert Fu

    IPC: H01L23/50 ,  G11C5/14

    CPC classification number: H01L29/0646 ,  G11C5/146 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/0203 ,  H01L27/0222 ,  H01L27/0928 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

    Abstract translation: 一种具有体偏置电压机构的集成电路器件。 集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。 可以可选地提供用于与第一外部设置的销连接的第一垫。 第一个焊盘用于接收外部施加的主体偏置电压。 用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。 如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。 电源电压可以在集成电路内部获得。

    Method for making chrome photo mask
    5.
    发明申请
    Method for making chrome photo mask 审中-公开
    制作镀铬光罩的方法

    公开(公告)号：US20060057472A1

    公开(公告)日：2006-03-16

    申请号：US10940714

    申请日：2004-09-15

    Applicant: Robert Fu Tsai

    Inventor： Robert Fu Tsai

    IPC: C23F1/00 ,  C25D5/02 ,  C23F3/00 ,  B44C1/22 ,  G03F1/00

    CPC classification number: C23F4/00 ,  C23C18/1605 ,  C23C18/1608 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/1879 ,  C23C18/52 ,  C23F1/02 ,  C25D5/022 ,  C25D5/48 ,  G03F1/46 ,  G03F1/54 ,  G03F1/68

    Abstract: A method for making a chrome photo-mask is disclosed. A photo-mask blank is activated with activator on its upper surface for electroless chrome plating Next, the activated photo-mask blank is then immersed in the electroless chrome plating solution for being coated with a thin chrome layer. The electroless chrome plating process will continue until a desired thickness is formed. Preferably, an electro-plating process is employed after the growth of an initial electroless chrome layer. Then, the photo-mask blank with the chrome layer is subject to oxidation for forming an antireflection layer on the chrome layer. After the antireflective layer is successively formed, a resist film is formed on the antireflective layer. The resist film is then patterned in accordance with the predetermined pattern. Next, the antireflective layer and the chromium layer are dry-etched or wet-etched through openings in the patterned resist film. The resist film is subsequently stripped to form the desired photo-mask.

    Abstract translation: 公开了一种制造铬光掩模的方法。 光刻掩模坯料在其上表面用活化剂激活用于无电镀铬接下来，将活化的光掩模坯料浸入无电镀铬溶液中以涂覆薄铬层。 无电镀铬工艺将持续直到形成所需的厚度。 优选地，在初始化学镀铬层生长之后采用电镀工艺。 然后，具有铬层的光掩模坯料经过氧化，以在铬层上形成抗反射层。 在连续形成抗反射层之后，在抗反射层上形成抗蚀剂膜。 然后根据预定图案对抗蚀剂膜进行图案化。 接下来，通过图案化的抗蚀剂膜中的开口对抗反射层和铬层进行干蚀刻或湿蚀刻。 随后剥离抗蚀剂膜以形成所需的光掩模。

    Selective coupling of voltage feeds for body bias voltage in an integrated circuit device
    7.
    发明授权
    Selective coupling of voltage feeds for body bias voltage in an integrated circuit device 有权
    在集成电路器件中选择性地耦合用于体偏置电压的电压馈送

    公开(公告)号：US08415730B2

    公开(公告)日：2013-04-09

    申请号：US12033840

    申请日：2008-02-19

    Applicant: James B Burr ,  Robert Fu

    Inventor： James B Burr ,  Robert Fu

    IPC: G11C5/14

    CPC classification number: H01L29/0646 ,  G11C5/146 ,  H01L21/823493 ,  H01L21/823892 ,  H01L23/481 ,  H01L27/0203 ,  H01L27/0222 ,  H01L27/0928 ,  H01L29/1095 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

    Abstract translation: 一种具有体偏置电压机构的集成电路器件。 集成电路包括设置在其中的电阻结构，用于选择性地将外部体偏置电压或电源电压耦合到偏置阱。 可以可选地提供用于与第一外部设置的销连接的第一垫。 第一个焊盘用于接收外部施加的主体偏置电压。 用于产生体偏置电压的电路可以耦合到第一焊盘，用于将体偏置电压耦合到设置在集成电路器件上的多个偏置阱。 如果没有提供外部施加的体偏置电压，则电阻结构自动将电源电压耦合到偏置阱。 电源电压可以在集成电路内部获得。

    Variable output charge pump circuit
    8.
    发明授权
    Variable output charge pump circuit 有权
    可变输出电荷泵电路

    公开(公告)号：US08350616B1

    公开(公告)日：2013-01-08

    申请号：US10712522

    申请日：2003-11-12

    Applicant: Robert Fu ,  Tien-Min Chen

    Inventor： Robert Fu ,  Tien-Min Chen

    IPC: G05F1/10 ,  G05F3/02

    CPC classification number: H02M3/07

    Abstract: A drive frequency source with two selectable output frequencies connected to two charge pump arrays. A first array of basic charge pump units is connected to the first output frequency and a second array of basic charge pump units is connected to the output frequency. One or more of the basic charge pump units making up the aforementioned first and second charge pump arrays has an enable input allowing its output current contribution to be added or subtracted from the total array output. The output of the first array is coupled to a P-type substrate and the output of the second array is coupled to an N-well residing in the P-type substrate. A controller may be coupled to the drive frequency source for selecting the output frequencies, and an output monitor may be coupled between the array outputs and the controller to provide feedback.

    Abstract translation: 具有两个可选输出频率的驱动频率源连接到两个电荷泵阵列。 基本电荷泵单元的第一阵列连接到第一输出频率，第二阵列的基本电荷泵单元连接到输出频率。 构成上述第一和第二电荷泵阵列的一个或多个基本电荷泵单元具有允许其输出电流贡献从总阵列输出相加或减去的使能输入。 第一阵列的输出耦合到P型衬底，并且第二阵列的输出耦合到位于P型衬底中的N阱。 控制器可以耦合到驱动频率源以选择输出频率，并且输出监视器可以耦合在阵列输出和控制器之间以提供反馈。

    System for substrate potential regulation during power-up in integrated circuits
    9.
    发明授权
    System for substrate potential regulation during power-up in integrated circuits 有权
    集成电路上电期间衬底电位调节系统

    公开(公告)号：US08022747B2

    公开(公告)日：2011-09-20

    申请号：US12628010

    申请日：2009-11-30

    Applicant: Robert Fu ,  Tien-Min Chen

    Inventor： Robert Fu ,  Tien-Min Chen

    IPC: H03K3/011

    CPC classification number: H01L27/0222 ,  H01L21/823892 ,  H01L29/78 ,  H03K2217/0018

    Abstract: An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

    Abstract translation: 在初始电源施加时，具有由开关协调的体偏置输入的集成电路。 耦合到集成电路的N阱偏压和P型衬底偏置线的开关根据偏置电源线的状态选择性地将衬底耦合到接地或衬底偏置电源。 在上电和初始施加N阱偏压期间，衬底耦合到地，以防止漏极引起衬底电位的上升。 在感测到衬底偏置线上的衬底偏置电位的存在之后，开关将衬底耦合到衬底偏置线而不是接地。 在另一个实施例中，开关通过感测电荷泵使能信号间接地感测到衬底偏置电位的可用性。

    SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS
    10.
    发明申请
    SYSTEM FOR SUBSTRATE POTENTIAL REGULATION DURING POWER-UP IN INTEGRATED CIRCUITS 有权
    在集成电路加电期间的基极电位调节系统

    公开(公告)号：US20100073075A1

    公开(公告)日：2010-03-25

    申请号：US12628010

    申请日：2009-11-30

    Applicant: Robert Fu ,  Tien-Min Chen

    Inventor： Robert Fu ,  Tien-Min Chen

    IPC: H03K3/01

    CPC classification number: H01L27/0222 ,  H01L21/823892 ,  H01L29/78 ,  H03K2217/0018

    Abstract: An integrated circuit with body-bias inputs coordinated by a switch at initial power application. A switch coupled to the N-well bias and P-type substrate bias lines of an integrated circuit selectively couples the substrate to ground or the substrate bias supply, depending upon the state of the bias supply lines. During power-up and the initial application of the N-well bias, the substrate is coupled to ground to prevent a leakage induce rise in the substrate potential. Upon sensing the presence of the substrate bias potential on the substrate bias line, the switch couples the substrate to the substrate bias line instead of ground. In another embodiment, a switch indirectly senses the availability of the substrate bias potential by sensing a charge pump enable signal.

    Abstract translation: 在初始电源施加时，具有由开关协调的体偏置输入的集成电路。 耦合到集成电路的N阱偏压和P型衬底偏置线的开关根据偏置电源线的状态选择性地将衬底耦合到接地或衬底偏置电源。 在上电和初始施加N阱偏压期间，衬底耦合到地，以防止漏极引起衬底电位的上升。 在感测到衬底偏置线上的衬底偏置电位的存在之后，开关将衬底耦合到衬底偏置线而不是接地。 在另一个实施例中，开关通过感测电荷泵使能信号间接地感测到衬底偏置电位的可用性。

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